Master of Engineering Balram Sahu - Embedded Sensing ...

35 5.2. Process Flow• To place and route, First standard cell library was modified as discussed in sectionsec:librarymodification and using this library, we synthesized our RTL code ofCORDIC algorithm at 200MHz clock speed.• Synthesis generates a gate level netlist, which gives us different cells used in thecomplete circuit and also number of occurrence of each cell. Using this information,average leakage power of each cell is calculated by simulating them individually incadence.• Total leakage power is calculated by adding average leakage power of all the cellsfor different supply voltage.• Timing analysis is done using Design compiler which gives us the critical path andassociated node capacitances in the critical path.• Extracted node capacitances does not include the wire capacitance. Since in subthresholdoperation wire load capacitance also play significant role, parasitic informationis extracted from the placed and routed SoC (using SoC Encounter) in theform of .spef file. This information is extracted for each node associated with thecritical path and added this parasitic capacitance to respective node.• This path is analyzed in cadence and total path delay is calculated for differentsupply voltage.• Now we have the total leakage power and critical path delay of circuit at supplyvoltage from 270mV to 1.2V. Following equations are used to calculate the powerand energy at all these voltage levels:T otalP ower(P T ) = DynamicP ower(P DY N ) + LeakageP ower(P LEAK )(5.1)= αC eff V 2 DDf + P LEAK (5.2)P T 1 = αC eff V 2 DD1f 1 + P LEAK1 (5.3)P T 2 = αC eff V 2 DD2f 2 + P LEAK2 (5.4)P DY N2 = P T 2 − P LEAK2 = V DD2 2 f 2VDD1 2 f .(P T 1 − P LEAK1 ) (5.5)1P T 2 = V DD2 2 f 2VDD1 2 f .(P T 1 − P LEAK1 ) + P LEAK2 (5.6)1LeakageEnergy(E LEAK ) = P LEAK2 .T D2 (5.7)DynamicEnergy(E DY N2 ) = P DY N2 .T D2 (5.8)