1. Basic Concepts in Reliability Design - nl3prc

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[2] Designing for Reliability3.1.3 Increasing Gate Oxide Reliability with Hydrogen-Annealed Interstitial WafersWhen high temperature heat treatment is applied to silicon wafers in a hydrogen atmosphere,interstitial oxygen on the surface layer diffuses in an outward direction resulting in significantlyfewer surface crystal defects (such defects are, in effect, oxygen deposits).Figure 3.3 (a) shows the evaluation results for a defect-free surface layer formed on a hydrogenannealedinterstitial (HAI) wafer formed by annealing a CZ wafer with hydrogen at 1200 °C for onehour. The oxygen deposits on the surface layer (technically known as bulk micro-defects or BMDs)have been greatly reduced.Advances in the fine-pattern processing of semiconductor devices have led to a reduction in gate oxidefilm thickness. The role that oxide film plays in the reliability of semiconductor devices calls forincreased reliability of the gate oxide film. With much fewer surface crystal defects on the HAI wafer,as shown in the diagram, the percentage of defects in mode B of the oxide film breakdown voltage canbe reduced (to zero). (See Figure 3.3 (b).)1E+07C+ Mode12 MV/cm or more1E+06CZ wafer100C- mode8∼12 MV/cmBMD density (cm -2 )1E+051E+041E+03Hydrogen annealing waferRate (%)806040B mode8 MV/cm or less1E+02201E+010 20 40 60 80 100 120Depth below surface (µm)0CZ Hydrogen annealingWafer(a) Depth distribution of crystal defects (BMDs)(b) Comparison of oxide film breakdown voltagesFigure 3.3 Effects of hydrogen-annealed wafer2-16
[2] Designing for Reliability3.2 Si-SiO 2 InterfaceSemiconductor chips based on the surface phenomenon exhibit certain characteristics which varysignificantly depending on the state of the Si-SiO 2 interface. There are many complicated failuremechanisms attributed to this phenomenon.Failure mechanisms related to the Si-SiO 2 interface can be classified into those induced by thesubstrate and those induced by the gate oxide film or surface protective film. The former are describedbelow. The latter are described in Section 3.3, Gate Oxide Film and Section 3.4, Passivation.3.2.1 Degradation Due to Hot Carriers 2)When voltage is applied to the drain of an N-channel MOS transistor, a large electrical field isgenerated in the drain region as shown in Figure 3.4. As carriers flow into this area, they gain energyfrom the electrical field and become hot carriers. Some of them are scattered by phonons and otherslose energy through impact ionization. Hot carriers with high enough energy to surmount the Si-SiO 2energy barrier are injected into the gate oxide film. This phenomenon, which accelerates withincreased voltage, changes the MOS transistor threshold voltage (V th ) and the transconductance (Gm).Depending on the bias condition of MOS transistor, the carriers injected into and trapped within thegate oxide film are referred to as channel hot electrons, drain avalanche hot carriers (DAHC),secondary hot electrons or substrate hot electrons. 3)To avoid the effects of hot carriers, countermeasures are taken, such as reducing the circuit’s internaloperating voltage or creating a gate oxide film which does not easily trap injected hot carriers. Variousmeasures are recommended for the transistor structure, especially for devices with a gate length ofless than 2 µm. One of these is the lightly doped drain (LDD) transistor, shown in Figure 3.5, whichexhibits a smaller electrical field around the drain and thus has fewer hot carriers. 4)Degradation of device characteristics due to hot carriers also occurs in bipolar transistors. This is awell-known phenomenon characterized by a reduced h FE when a reverse bias is applied across theemitter-base. With the appearance of advanced shallow junction devices in recent years, there is atendency towards increased reverse leakage current between the emitter and base and therefore atendency towards greater degradation of characteristics due to hot carriers. Figure 3.6 shows anexample of a degraded high-frequency characteristic (f t ) caused by reverse emitter-base bias. This isbecause the base current increases due to an increased number of recombination centers at the Si-SiO 2 interface caused by hot-carrier injection during reverse biasing.Most semiconductor failure modes exhibit higher degradation rates at higher temperatures. The hotcarriereffect, however, accelerates as the temperature decreases.2-17
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