1. Basic Concepts in Reliability Design - nl3prc

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[2] Designing for Reliability3.4 PassivationPassivation has three primary objectives:1 Stabilization of the Si surface2 Creation of an interlayer insulating film in multilayered structures3 Protection of the entire chipDefects in passivation often lead to catastrophic failures. Such failures include unstable deviceoperation caused by changes in film properties, instability, pin holes and cracks, and Al metal opens orcorrosion due to degradation and stress. These factors are important when device reliability isconsidered. Symptoms of instability and degradation due to defective passivation include V th shift andfield leakage in MOS transistors, decreased h FE in bipolar transistors, and breakdown voltagedegradation in PN junctions.These types of failure mode are known to be caused by the following mechanisms:1 Ion contamination2 Polarization3 Parasitic MOS due to lateral extension of the electrical field4 Corrosion of Al metal due to phosphorous in PSG, fluorine in plasma CVD oxide film or moisturepenetration5 Pin holes and cracks6 Stress7 Chip degradation due to degass 9)3.4.1 Ion ContaminationContamination by Na + and other mobile ions introduced into the passivation or into the interfaceduring the manufacturing process greatly affect device reliability.The Na + ions are deactivated by phosphide gettering. However, application of an electrical field cancause them to move into the passivation oxide film and collect in the field region, gate region oraround the PN junction, resulting in failures due to parasitic MOS, V th change, breakdown voltagedegradation etc. Breakdown voltage degradation can be recovered from by baking without bias. Likeelectrical field strength and temperature, humidity also accelerates degradation due to ioncontamination.Figure 3.10 shows experimental results for the external ion-blocking capability of phosphosilicateglass (PSG) with various film thicknesses and phosphorous contents. 10) In the experiment, the testelement group (TEG) device structure shown in Figure 3.11 was used on the assumption that ionicimpurities from the mold resin pass through the PSG film and are accumulated on the gate oxide filmwhich has no gate electrodes. This phenomenon causes a channel leakage current to flow between thedrain and source whose level and variation with time are an indication of the ion-blocking effect of thepassivation film. It can be understood from Figure 3.10 that the blocking effect increases withincreased film thickness or phosphorous content. This rise in leakage current in the early stage can be2-22
[2] Designing for Reliabilityseen in the case of high phosphorous concentration. This is thought to be caused by ionic conductionaccompanied by PSG moisture absorption.The above-mentioned observations show why PSG is very often used for passivation. However, asevident from the experimental results, ionic degradation cannot be completely blocked, even usingPSG. For this reason, silicon nitride film on PSG film, with its superior ion-blocking effect, is beingused. Toshiba has also developed a nitride self-alignment (NSA) process to minimize ionic problems inbipolar ICs.IDS (mA)1010.10.01t PSG8: 0.3 µs9: 0.5 µs10: 0.8 µs4: 1.2 µsat 85°CResin: FV D = 10 V89104IDS (mA)1010.10.01Relative amountof phosphorous1: 02: 0.703: 0.864: 1.005: 1.256: 1.437: 1.60Resin: Ft PSG = 3 µs∼11 µsat 85°C V D = 10 V1276450.0011010 210 3Time (minutes)10 50.0011010 210 4 (b) Effect of phosphorous content on I DS variation10 310 4Time (minutes)310 5(a)Effect of PSG film thickness on I DSvariation due to agingdue to agingFigure 3.10 Results of test of PSG ion-blocking effectResinPSGN +I DSN +Gate oxideP wellI DSV DFigure 3.11 Structure of TEG device used in evaluation of PSG ion-blocking effectFigure 3.12 compares the h FE shift for the NSA process with the conventional process for bipolartransistors, using a high-temperature reverse bias test. 11) The NSA process exhibits no h FE shift.DIP16, Plastic Package1.1NSA transistorhFE (BT)/hFE (BT = 0)1.00.90.80.715V1 nA1 µA1 mAConventionaltransistor24 48 96250 500 1000BT time (hours)Figure 3.12 Change in current amplification factor (h FE ) during high-temperature reverse bias test2-23
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