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CC1101incremented by one each new byte (every 8clock pulses). The burst access is either aread or a write access and must be terminatedby setting CSn high.For register addresses in the range 0x30-0x3D, the burst bit is used to select betweenstatus registers, burst bit is one, and commandstrobes, burst bit is zero (see 10.4 below).Because of this, burst access is not availablefor status registers and they must be accessesone at a time. The status registers can only beread.10.3 SPI ReadWhen reading register fields over the SPIinterface while the register fields are updatedby the radio hardware (e.g. MARCSTATE orTXBYTES), there is a small, but finite,probability that a single read from the registeris being corrupt. As an example, theprobability of any single read from TXBYTESbeing corrupt, assuming the maximum datarate is used, is approximately 80 ppm. Refer tothe CC1101 Errata Notes [1] for more details.10.4 Command StrobesCommand Strobes may be viewed as singlebyte instructions to CC1101. By addressing acommand strobe register, internal sequenceswill be started. These commands are used todisable the crystal oscillator, enable receivemode, enable wake-on-radio etc. The 13command strobes are listed in Table 34 onpage 60.The command strobe registers are accessedby transferring a single header byte (no data isbeing transferred). That is, only the R/W¯ bit,the burst access bit (set to 0), and the sixaddress bits (in the range 0x30 through 0x3D)are written. The R/W¯ bit can be either one orzero and will determine how theFIFO_BYTES_AVAILABLE field in the statusbyte should be interpreted.When writing command strobes, the statusbyte is sent on the SO pin.A command strobe may be followed by anyother SPI access without pulling CSn high.However, if an SRES strobe is being issued,one will have to waith for SO to go low againbefore the next header byte can be issued asshown in Figure 8. The command strobes areexecuted immediately, with the exception ofthe SPWD and the SXOFF strobes that areexecuted when CSn goes high.Figure 8: SRES Command Strobe10.5 FIFO AccessThe 64-byte TX FIFO and the 64-byte RXFIFO are accessed through the 0x3F address.When the R/W¯ bit is zero, the TX FIFO isaccessed, and the RX FIFO is accessed whenthe R/W¯ bit is one.The TX FIFO is write-only, while the RX FIFOis read-only.The burst bit is used to determine if the FIFOaccess is a single byte access or a burstaccess. The single byte access methodexpects a header byte with the burst bit set tozero and one data byte. After the data byte anew header byte is expected; hence, CSn canremain low. The burst access method expectsone header byte and then consecutive databytes until terminating the access by settingCSn high.The following header bytes access the FIFOs:• 0x3F: Single byte access to TX FIFO• 0x7F: Burst access to TX FIFO• 0xBF: Single byte access to RX FIFO• 0xFF: Burst access to RX FIFOWhen writing to the TX FIFO, the status byte(see Section 10.1) is output for each new databyte on SO, as shown in Figure 7. This statusbyte can be used to detect TX FIFO underflowwhile writing data to the TX FIFO. Note thatthe status byte contains the number of bytesfree before writing the byte in progress to theTX FIFO. When the last byte that fits in the TXFIFO is transmitted on SI, the status bytereceived concurrently on SO will indicate thatone byte is free in the TX FIFO.The TX FIFO may be flushed by issuing aSFTX command strobe. Similarly, a SFRXcommand strobe will flush the RX FIFO. ASFTX or SFRX command strobe can only beissued in the IDLE, TXFIFO_UNDERLOW, orRXFIFO_OVERFLOW states. Both FIFOs areflushed when going to the SLEEP state.SWRS061C Page 26 of 94
CC1101Figure 9 gives a brief overview of differentregister access types possible.10.6 PATABLE AccessThe 0x3E address is used to access thePATABLE, which is used for selecting PApower control settings. The SPI expects up toeight data bytes after receiving the address.By programming the PATABLE, controlled PApower ramp-up and ramp-down can beachieved, as well as ASK modulation shapingfor reduced bandwidth. See SmartRF ® Studio[7] for recommended shaping / PA rampingsequences.See Section 24 on page 49 for details onoutput power programming.The PATABLE is an 8-byte table that definesthe PA control settings to use for each of theeight PA power values (selected by the 3-bitvalue FREND0.PA_POWER). The table iswritten and read from the lowest setting (0) tothe highest (7), one byte at a time. An indexcounter is used to control the access to thetable. This counter is incremented each time abyte is read or written to the table, and set tothe lowest index when CSn is high. When thehighest value is reached the counter restartsat zero.The access to the PATABLE is either singlebyte or burst access depending on the burstbit. When using burst access the index counterwill count up; when reaching 7 the counter willrestart at 0. The R/W¯ bit controls whether theaccess is a read or a write access.If one byte is written to the PATABLE and thisvalue is to be read out then CSn must be sethigh before the read access in order to set theindex counter back to zero.Note that the content of the PATABLE is lostwhen entering the SLEEP state, except for thefirst byte (index 0).Figure 9: Register Access Types11 Microcontroller Interface and Pin ConfigurationIn a typical system, CC1101 will interface to amicrocontroller. This microcontroller must beable to:• Program CC1101 into different modes• Read and write buffered data• Read back status information via the 4-wireSPI-bus configuration interface (SI, SO,SCLK and CSn).11.1 Configuration InterfaceThe microcontroller uses four I/O pins for theSPI configuration interface (SI, SO, SCLK andCSn). The SPI is described in Section 10 onpage 23.11.2 General Control and Status PinsThe CC1101 has two dedicated configurablepins (GDO0 and GDO2) and one shared pin(GDO1) that can output internal statusinformation useful for control software. Thesepins can be used to generate interrupts on theMCU. See Section 30 page 55 for more detailson the signals that can be programmed.GDO1 is shared with the SO pin in the SPIinterface. The default setting for GDO1/SO is3-state output. By selecting any other of theprogramming options, the GDO1/SO pin willbecome a generic pin. When CSn is low, thepin will always function as a normal SO pin.In the synchronous and asynchronous serialmodes, the GDO0 pin is used as a serial TXdata input pin while in transmit mode.SWRS061C Page 27 of 94
Page 1 and 2: 6789CC1101CC1101Low-Cost Low-Power
Page 3 and 4: CC1101AbbreviationsAbbreviations us
Page 5 and 6: CC110115.3 PACKET FILTERING IN RECE
Page 7 and 8: CC11011 Absolute Maximum RatingsUnd
Page 9 and 10: CC1101Parameter Min Typ Max Unit Co
Page 15 and 16: CC11014.7 Analog Temperature Sensor
Page 17 and 18: CC1101Pin # Pin Name Pin type Descr
Page 19 and 20: CC1101Table 14: Overview of Externa
Page 22 and 23: CC1101Default state when the radio
Page 24 and 25: CC1101transfer the header byte. Thi
Page 28 and 29: CC1101The GDO0 pin can also be used
Page 30 and 31: CC110113 Receiver Channel Filter Ba
Page 32 and 33: CC110115.1 Data WhiteningFrom a rad
Page 34 and 35: CC1101• Transmit at least 345 byt
Page 36 and 37: CC1101MISO line each time a header
Page 38 and 39: CC1101Data rate [kBaud] RSSI_offset
Page 40 and 41: CC1101MAX_DVGA_GAIN value. This wil
Page 42 and 43: CC110119 Radio ControlSIDLECAL_COMP
Page 44 and 45: CC110119.3 Voltage Regulator Contro
Page 46 and 47: CC1101DescriptionXOSCPeriods26 MHzC
Page 48 and 49: CC110121 Frequency ProgrammingThe f
Page 50 and 51: CC1101OutputPower[dBm]Setting315 MH
Page 52 and 53: CC110126 SelectivityFigure 24 to Fi
Page 54 and 55: CC1101Component C L = 10 pF C L = 1
Page 56 and 57: CC1101GDOx_CFG[5:0] Description0 (0
Page 58 and 59: CC110132.2 Frequency Hopping and Mu
Page 60 and 61: CC110133 Configuration RegistersThe
Page 62 and 63: CC1101Address Register Description
Page 64 and 65: CC1101Table 37: SPI Address Space33
Page 66 and 67: CC11010x06: PKTLEN - Packet LengthB
Page 68 and 69: CC11010x0B: FSCTRL1 - Frequency Syn
Page 70 and 71: CC11010x12: MDMCFG2 - Modem Configu
Page 72 and 73: CC11010x15: DEVIATN - Modem Deviati
Page 74 and 75: CC11010x17: MCSM1- Main Radio Contr
Page 76 and 77:
CC11010x19: FOCCFG - Frequency Offs
Page 78 and 79:
CC11010x1B: AGCCTRL2 - AGC ControlB
Page 80 and 81:
CC11010x1D: AGCCTRL0 - AGC ControlB
Page 82 and 83:
CC11010x21: FREND1 - Front End RX C
Page 84 and 85:
CC110133.2 Configuration Register D
Page 86 and 87:
CC11010x35 (0xF5): MARCSTATE - Main
Page 88 and 89:
CC11010x3D (0xFC): RCCTRL0_STATUS -
Page 90 and 91:
CC110134.5 Carrier Tape and Reel Sp
Page 92 and 93:
CC110137 General Information37.1 Do
Page 94 and 95:
CC1101AsiaPhone International +886-
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