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CC110123 Voltage RegulatorsCC1101 contains several on-chip linear voltageregulators, which generate the supply voltageneeded by low-voltage modules. Thesevoltage regulators are invisible to the user, andcan be viewed as integral parts of the variousmodules. The user must however make surethat the absolute maximum ratings andrequired pin voltages in Table 1 and Table 13are not exceeded. The voltage regulator forthe digital core requires one externaldecoupling capacitor.24 Output Power ProgrammingThe RF output power level from the devicehas two levels of programmability, asillustrated in Figure 22. Firstly, the specialPATABLE register can hold up to eight userselected output power settings. Secondly, the3-bit FREND0.PA_POWER value selects thePATABLE entry to use. This two-levelfunctionality provides flexible PA power rampup and ramp down at the start and end oftransmission, as well as ASK modulationshaping. All the PA power settings in thePATABLE from index 0 up to theFREND0.PA_POWER value are used.The power ramping at the start and at the endof a packet can be turned off by settingFREND0.PA_POWER to zero and thenprogram the desired output power to index 0 inthe PATABLE.Setting the CSn pin low turns on the voltageregulator to the digital core and starts thecrystal oscillator. The SO pin on the SPIinterface must go low before the first positiveedge of SCLK. (setup time is given in Table16).If the chip is programmed to enter power-downmode, (SPWD strobe issued), the power will beturned off after CSn goes high. The power andcrystal oscillator will be turned on again whenCSn goes low.The voltage regulator output should only beused for driving the CC1101.If OOK modulation is used, the logic 0 andlogic 1 power levels shall be programmed toindex 0 and 1 respectively.Table 30 contains recommended PATABLEsettings for various output levels andfrequency bands. Using PA settings from 0x61to 0x6F is not recommended. See Section10.6 on page 27 for PATABLE programmingdetails.Table 31 contains output power and currentconsumption for default PATABLE setting(0xC6). PATABLE must be programmed inburst mode if you want to write to other entriesthan PATABLE[0].Note that all content of the PATABLE, exceptfor the first byte (index 0) is lost when enteringthe SLEEP state.SWRS061C Page 49 of 94