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CC1101the optional address byte). If addressrecognition is enabled on the receiver, thesecond byte written to the TX FIFO must bethe address byte. If fixed packet length isenabled, then the first byte written to the TXFIFO should be the address (if the receiveruses address recognition).The modulator will first send the programmednumber of preamble bytes. If data is availablein the TX FIFO, the modulator will send thetwo-byte (optionally 4-byte) sync word andthen the payload in the TX FIFO. If CRC isenabled, the checksum is calculated over allthe data pulled from the TX FIFO and theresult is sent as two extra bytes following thepayload data. If the TX FIFO runs emptybefore the complete packet has beentransmitted, the radio will enterTXFIFO_UNDERFLOW state. The only way toexit this state is by issuing an SFTX strobe.Writing to the TX FIFO after it has underflowedwill not restart TX mode.If whitening is enabled, everything followingthe sync words will be whitened. This is donebefore the optional FEC/Interleaver stage.Whitening is enabled by settingPKTCTRL0.WHITE_DATA=1.If FEC/Interleaving is enabled, everythingfollowing the sync words will be scrambled bythe interleaver and FEC encoded before beingmodulated. FEC is enabled by settingMDMCFG1.FEC_EN=1.15.5 Packet Handling in Receive ModeIn receive mode, the demodulator and packethandler will search for a valid preamble andthe sync word. When found, the demodulatorhas obtained both bit and byte synchronismand will receive the first payload byte.If FEC/Interleaving is enabled, the FECdecoder will start to decode the first payloadbyte. The interleaver will de-scramble the bitsbefore any other processing is done to thedata.If whitening is enabled, the data will be dewhitenedat this stage.When variable packet length mode is enabled,the first byte is the length byte. The packethandler stores this value as the packet lengthand receives the number of bytes indicated bythe length byte. If fixed packet length mode isused, the packet handler will accept theprogrammed number of bytes.Next, the packet handler optionally checks theaddress and only continues the reception if theaddress matches. If automatic CRC check isenabled, the packet handler computes CRCand matches it with the appended CRCchecksum.At the end of the payload, the packet handlerwill optionally write two extra packet statusbytes (see Table 21 and Table 22) that containCRC status, link quality indication, and RSSIvalue.15.6 Packet Handling in FirmwareWhen implementing a packet oriented radioprotocol in firmware, the MCU needs to knowwhen a packet has been received/transmitted.Additionally, for packets longer than 64 bytesthe RX FIFO needs to be read while in RX andthe TX FIFO needs to be refilled while in TX.This means that the MCU needs to know thenumber of bytes that can be read from orwritten to the RX FIFO and TX FIFOrespectively. There are two possible solutionsto get the necessary status information:a) Interrupt Driven SolutionIn both RX and TX one can use one of theGDO pins to give an interrupt when a syncword has been received/transmitted and/orwhen a complete packet has beenreceived/transmitted(IOCFGx.GDOx_CFG=0x06). In addition, thereare 2 configurations for theIOCFGx.GDOx_CFG register that areassociated with the RX FIFO(IOCFGx.GDOx_CFG=0x00andIOCFGx.GDOx_CFG=0x01) and two that areassociated with the TX FIFO(IOCFGx.GDOx_CFG=0x02andIOCFGx.GDOx_CFG=0x03) that can be usedas interrupt sources to provide information onhow many bytes are in the RX FIFO and TXFIFO respectively. See Table 33.b) SPI PollingThe PKTSTATUS register can be polled at agiven rate to get information about the currentGDO2 and GDO0 values respectively. TheRXBYTES and TXBYTES registers can bepolled at a given rate to get information aboutthe number of bytes in the RX FIFO and TXFIFO respectively. Alternatively, the number ofbytes in the RX FIFO and TX FIFO can beread from the chip status byte returned on theSWRS061C Page 35 of 94