Beyond Bits VII - Freescale Semiconductor

BeyondBits 

Issue 7 

VYBRID EDITION 

Rich applications 

in real time 

INTRODUCING 

Vybrid Controller 

Solutions 

March 2012

Introducing Vybrid 

Controller Solutions 

Rich applications in real time 

freescale.com/Vybrid 

Welcome to the latest edition of Beyond Bits, created to help you bring your innovative 

design ideas to life. 

This edition provides an in-depth look at our Vybrid portfolio of controller solutions, designed to dramatically 

simplify solutions that need rich human-machine interface (HMI) and connectivity concurrent with real-time 

control and response. We’re taking the concept of a total embedded solution approach further, and helping 

you bring differentiated products to market faster. Complex embedded systems must continue to operate 

consistently and predictably. The Vybrid brand is distinguished by software tightly coupled with silicon— 

enabling concurrent low-latency communication between high-level operating systems such as Linux and 

real-time operating systems (RTOS) like MQX. We realize that the majority of product development time 

lies in getting the software right. Starting with the Vybrid portfolio, we will release software virtual models of 

silicon to help you begin software development before silicon is available—shortening the cycle of time to 

revenue. 

The Vybrid family provides unprecedented system integration, starting with a unique heterogeneous 

architecture that brings together ARM ® Cortex-A and ARM Cortex-M cores as well as a powerful array 

of peripherals. Extensive communication and memory options, as well as support for external peripherals and 

memory, are available. Security and data integrity has been carefully considered, with features for safeguarding 

memory, content management and communication. HMI and multimedia options include audio interfaces, 

dual display controllers, video interface and OpenVG GPU for UI acceleration. 

The Vybrid portfolio also provides a broad offering of supporting resources, including reference designs, 

application notes, white papers, on-demand training, board support packages and middleware. We also 

provide a way to ease early software development by releasing a software virtual model, as well as IDE tool 

support such as our Eclipse-based CodeWarrior Development Studio with Processor Expert, ARM DS-5 and 

the modular Tower System development platform. This support, along with the vast resources of the ARM and 

open-source communities, will help simplify your design process and reduce your time to market. 

Our extensive range of 8-, 16- and 32-bit MCUs and MPUs offers solutions you can trust. You can count 

on us to deliver industry-leading vertical solutions, scalable product lines, intellectual property and process 

technology roadmaps, outstanding technical support, a robust ecosystem and 

a broad range of devices, available for a minimum of 10 years.* 

Thank you for considering Freescale solutions for your next-generation design. We look forward to 

working with you. 

Regards, 

Reza Kazerounian 

Senior Vice President and General Manager 

Automotive, Industrial and Multi-Market Solutions Group 

Freescale Semiconductor 

*For Terms and Conditions and to obtain a list of available products, visit freescale.com/productlongevity. 

Vybrid Controller Solutions 

1

Vybrid Family Overview 

4 Vybrid Controller Solutions 

8 Vybrid VF3xx Family 





Technical Highlights 

19 Core Technology 

22 Multicore Communication 

24 Multimedia Subsystem 

27 Security Subsystem 

29 Power Management 

31 Ethernet Subsystem 

33 USB Subsystem 

35 Memory Subsystem 

39 Universal Asynchronous Receiver/Transmitter 

Software and Development Tools 

42 Freescale Virtual Hardware Platform 

44 Freescale MQX Software Solutions 

48 Freescale Tower System 

50 Swell PEG Product Line 

51 Timesys LinuxLink 

52 CodeWarrior Development Studio 

54 DS-5 

56 IAR Embedded Workbench 

58 Atollic 

59 Multilink and Cyclone 

60 SEGGER: J-Link and Flasher 

61 SEGGER: RTOS, GUI and Middleware 

62 Lauterbach 

Table of Contents

Vybrid Family of Products



A unique heterogeneous platform solution 

The increasing complexity and 

demands of embedded systems 

creates greater need for sophisticated 

human-machine interfaces (HMI) 

and multiple connectivity options 

with safe, secure and predictable 

operation. To concurrently provide 

rich HMI and real-time control means 

bringing together two very different 

system paradigms. For example, HMI 

computation focuses on efficiently 

processing pixels and displaying 

them on a screen, while guaranteed 

determinism requires highly 

predictable response times for tasks. 

A traditional systems-level solution for 

such divergent needs would combine 

different pieces of silicon, such as 

an applications MPU and a real-time 

MCU, on a board. It would also require 

developing software and a protocol to 

enable simultaneous communication 

between real-time control and rich 

HMI. Application developers face a 

tremendous challenge of seamlessly 

integrating these diverse technologies 

in a single system. 

Our Vybrid portfolio brings to market 

a unique, low-power system solution 

that provides customers a way to 

combine rich applications requiring 

high-resolution graphical displays 

and connectivity with real-time 

determinism. The Vybrid portfolio 

enables customers to create systems 

that concurrently run a high-level 

operating system such as Linux ® 

and a real-time operating system 

such as MQX on the same device. 

This, along with a communication 

API between the rich domain and the 

real-time domain and a tool chain 

4 

Vybrid Portfolio Key Attributes 

Total 

System 

Solution 

Optimal 

System 

Performance 

that eases debug of such systems, 

dramatically shortens customer time 

to revenue. The families in the Vybrid 

portfolio span entry-level products for 

customers who want to upgrade from 

the Kinetis MCU to devices with large 

on-chip SRAM up to highly integrated, 

heterogeneous dual-core solutions 

that can serve industrial and consumer 

markets. 

Each device in the Vybrid portfolio 

offers a rich suite of reference designs, 

app notes, board support packages 

and middleware for its market space. 

This, along with the vast resources 

Rich Apps in Real Time 

Unprecedented 

System 

Integration 

Low-Power 

Process 

of Freescale, ARM ® and open-source 

communities, will help customers 

to develop software solutions and 

support for their applications and 

dramatically reduce time to market. 

Scalable and Compatible 

across Multiple Cores 

Vybrid devices have a dual core 

architecture that combines the ARM 

Cortex-A5 application processor and 

the ARM Cortex-M4 for real-time 

control. The Vybrid portfolio is designed 

to be compatible with Kinetis MCUs 

featuring the ARM Cortex-M4 core and 

the i.MX6 series featuring the ARM 

Cortex-A9 core, while also providing

Back to Table of Contents Beyond Bits Vybrid Edition 

Vybrid Family Details 

Vybrid 

Families DDR 

VF7xx Family 

[Heterogenous Dual Core] 

ARM ® Cortex-A5 up to 500 MHz 

ARM Cortex-M4 up to 167 MHz 

364-pin MAPBGA 

VF6xx Family 

[Heterogenous Dual Core] 

ARM Cortex-A5 up to 500 MHz 

ARM Cortex-M4 up to 167 MHz 


VF5xx Family 



VF4xx Family 



VF3xx Family 


176-pin LQFP 


Camera Interface 

Video ADC 

Common Platform, Analog and Digital 

CRC and TZ Address 

12-bit ADC 

Space Controllers 

I 2 C 12-bit DAC 

Programmable 

Delay Block 

USB Host w/PHY 

USB OTG w/PHY 

Segment LCD 

TFT LCD (w/ 

Touch Screen) 

Ethernet 

Controller 

L2 Switch 

Security (HAB, 

Tamper, Det.) 

External Bus 

Y 2 

1 

Y 

Y 

Secure JTAG 

Flash Controller Secure Fuses 

UARTs Timers 

Low-Voltage, 

Low-Power Multiple 

Operating Modes, 

Clock Gating 

(1.73V–3.6V) 

Secure RAM 

eSDHC 

DMA 

ESAI SRAM 

2 

2 

2 

Tools 

Packaged IDE 

Packaged OS 

and Multicore 

Communication API 

Application Software 

Ind. Protocols, 

Peripheral Drivers 

Broad Third-Party 

Ecosystem Support 

Y 

Y 

scalable devices that can address the 

needs of a market that demands critical 

safety and security, connectivity and 

rich HMI in the same piece of silicon. 

The Vybrid roadmap is built with this 

scalability and code compatibility in 

mind so that the performance of the 

device roadmap grows with customers‘ 

needs long into the future. 

One of the key benefits of the Vybrid 

heterogeneous architecture that 

combines the ARM Cortex-A5 core 

with the ARM Cortex-M4 core is the 

partitioning of tasks based on their 

characteristics. For tasks that need 

predictable interrupt management, 

for example, a typical need for realtime 

applications, the Vybrid platform 

has the ARM Cortex-M4 core with 

a Nested Vector Interrupt Controller 

(NVIC) while allowing graphical 

applications and connectivity stacks 

to be run on the ARM Cortex-A5 

applications processor. 

Software can be segmented so that 

tasks that need predictable latencies 

can be run on the ARM Cortex-M4 

core and computer intensive processes 

run on the ARM Cortex-A5 core. 

Total System Solution 

Vybrid devices take a total system 

approach. Complementing the lowpower 

silicon is a reference Linux BSP, 

a full-featured MQX RTOS, reference 

MQX BSP and a processor-toprocessor 

communication API that lets 

customers partition their code between 

the ARM Cortex-A5 (e.g., running 

Linux) and ARM Cortex-M4 (e.g., 

running MQX) to implement the lowest 

power solution for their application 

demands. In addition, customers 

have access to industry-leading IDE 

tool chains such as CodeWarrior 

with Processor Expert, ARM DS-5 

and IAR. A selection of connectivity, 

motor control, LCD, security stacks 

5

Vybrid Family Back to Table of Contents 

and drivers is also available. Vybrid 

devices are supported by Freescale’s 

Tower System, offering the flexibility 

to easily scale and expand customer 

designs based on market need. Tower 

Systems allow rapid prototyping in a 

development platform that maximizes 

hardware reuse and speeds time to 

market. 

Vybrid devices also accelerate time 

to market by providing a range of 

on-demand resources including 

reference designs, application notes, 

white papers and training to assist in 

implementing designs. 

Low-Power Process 

One of the critical foundational pieces 

of the Vybrid platform is its low-power 

process technology. The devices in this 

portfolio are fabricated in the 40 nm 

low-power process. The static leakage 

of the 40 nm LP process is 2x less 

than 65 nm and almost 3x less than 90 

nm. This enables more integration for a 

6 

Process Technology Node Comparison 

Technology Node 

90LP 

65LP 55LP 40LP 

Active Power Standby Power Speed 

given power envelope thus dissipating 

much less power for the same device. 

Unprecedented System 

Integration 

The Vybrid platform has an 

unprecedented level of system 

integration for a solution of its class. 

The centerpiece is the core complex 

featuring the ARM Cortex-A5 and 

ARM Cortex-M4 cores. 

ARM Cortex-A5 Core 

The ARM Cortex-A5 processor is a 

high-performance, low-power core 

with an L1 and L2 cache subsystem 

that provides full virtual memory 

capabilities, double precision floatingpoint 

unit (FPU) and the NEON media 

processing engine. It is intended 

as an upgrade for the ARM9 ® and 

ARM11 ® cores and is architecturally 

compatible with Cortex-A9. The 

ARM Cortex-A5 also has TrustZone ® 

Technology for creating secure 

applications. 

ARM Cortex-M4 Core 

The ARM Cortex-M4 core retains all the 

advantages of the ARM Cortex-M3 

core with an NVIC which gives 

deterministic interrupt handling capability 

demanded by real-time applications. 

The ARM Cortex-M4 adds digital signal 

processing capability in the form of 

DSP and SIMD instruction extensions, 

a single cycle MAC unit and single 

precision FPU. In addition, Freescale 

has added a direct memory access 

(DMA) controller, crossbar switch, L1 

on-chip cache memories and tightly 

coupled memories (TCM) which 

maximize processor performance and 

bus bandwidth. 

Communication Interfaces 

Vybrid devices feature a number of 

connectivity peripherals, including 

dual USB 2.0 (Low-, Full- and High- 

Speed) device/host/On-The-Go 

with integrated PHYs, dual 10/100 

Ethernet with Layer 2 Ethernet 

switch with IEEE ® 1588 hardware 

time stamping and reduced media 

independent interface (RMII) support 

for real-time industrial control. Multiple 

serial interfaces include UARTs with 

support for ISO7816 SIM/smart cards, 

SPI and I 2 C, while dual CAN modules 

enable industrial network bridging. 

Support for External Peripherals 

and Memory 

In addition to having up to 1.5 MB 

of on-chip SRAM for speedy code 

and data execution, Vybrid devices 

can interface to a variety of external 

peripherals and memories for system 

expansion and data storage. Dual 

Quad SPI interfaces with eXecute-in- 

Place (XiP) support can interface with 

the latest flash memory to offer up to 

160 MB/s of throughput. This allows 

for a very powerful single-chip solution 

when the large DDR memory sizes 

are not required. A secure digital host 

controller supports SD, SDIO, MMC

Back to Table of Contents 

or CE-ATA cards for in-application 

software upgrades, media files or 

adding Wi-Fi ® support. For interfacing 

to external peripherals such as 

external SRAM, EEPROM and other 

peripherals, a FlexBus external bus 

interface is provided. NAND flash and 

DRAM controllers with ECC support 

allow connection to a wide variety of 

memory types for critical applications. 

Battery-backed RAM is critical for 

secure systems to store authentication 

keys; Vybrid devices provide 16 KB 

of secure RAM. The platform also 

provides 96 KB ROM used for high 

assurance boot (HAB). 

Multimedia Options 

The Vybrid platform offers a host 

of multimedia options enabling 

customers to run rich applications with 

real-time control. 

Audio 

Three different types of audio 

interfaces are supported: synchronous 

audio interface (SAI) for full-duplex 

audio transfer, enhanced serial audio 

interface (ESAI) that is also full duplex 

and adds support for interfacing with 

SPDIF transceivers and the Sony/ 

Philips Digital Interface (SPDIF) for 

digital audio support. 

Display Controller 

Two independent display controller 

units (DCU) interface with TFT LCD 

displays. The DCU can drive LCD 

displays up to a resolution of XGA 

(1024x768). Also included is a 

segment LCD controller. 

Video Interface Unit (VIU) 

For image and vision capture, a VIU 

provides a 24-bit parallel interface for 

digital video. In addition, an optional 

video ADC will convert composite 

video into digital format. 


OpenVG Graphics 

Processing Unit 

Vivante GC355 OpenVG graphics 

accelerator supporting OpenVG1.1 

can be used for UI acceleration. 

Reliability, Safety and Security 

Vybrid devices include a variety of 

data integrity and security hardware 

features for safeguarding memory, 

communication and system data. 

A cyclic redundancy check module 

is available for validating memory 

contents and communication 

data, while a memory protection 

unit provides data protection and 

increased software reliability. For 

failsafe applications, an independently 

clocked watchdog offers protection 

against runaway code. When it comes 

to security, a hardware encryption 

unit supports several encryption 

and hashing algorithms for program 

validation as well as authentication 

and securing data for transfer and 

storage. The system security module 

includes a unique chip identifier, 

secure key storage and a hardware 

tamper detection system. The tamper 

detection system has integrated 

sensors for voltage, frequency, 

temperature and external sensing for 

physical attack detection. 

Optimal System 

Performance 

Vybrid devices are ideal for modern 

industrial applications that require 

higher integration of communication 

and connectivity interfaces, as well as 

HMI and UI acceleration. Customers 

can easily take full advantage of all 

the integrated Vybrid features to 

create differentiated products by 

leveraging the provided reference 

board support packages (BSP) for 

high-level operating systems (such 

as Linux) and real-time operating 

systems (such as MQX), which 

Beyond Bits Vybrid Edition 

include libraries and media framework 

tuned to the silicon architecture. 

The combination of high-efficiency 

silicon design, low-leakage process 

technology and software tuned for 

the silicon architecture results in 

low power consumption, eliminating 

the need for a fan or heat sink and 

helping to lower overall system BOM 

cost. As an example, because the 

platform architecture partitions tasks 

between the applications processor 

and the deterministic MCU, the ARM 

Cortex-M4 core helps to improve 

efficiency in industrial motor control 

applications which can result in a 

reduced carbon footprint. 

Vybrid Product Families 

The first five Vybrid families for 

industrial and consumer applications 

are scheduled to sample in Q3 

of 2012 with production planned 

for late Q4 2012 and early 2013. 

Vybrid products are built around a 

common set of system, analog and 

digital IP blocks. The devices in each 

product family are distinguishable 

by their performance and peripheral 

capabilities as shown in the “Vybrid 

Family Details” table on page 5. 

7


Vybrid VF3xx Family 

Single-chip solution with dual XiP Quad SPI, dual Ethernet and 

L2 switch for appliances and energy control 

The VF3xx family is 

the entry point into the 

Vybrid portfolio and features 

the ARM ® Cortex-A5 core. 

It provides an efficient 

solution for an applications 

processor with 1.5 MB of 

on-chip SRAM and a rich 

suite of communication, 

connectivity and humanmachine 

interfaces (HMI). 

Target Applications 

• Home energy automation 

• Low-end appliances 

• Portable patient monitors 

• Metering data concentrators 

Mixed-Signal Capability 

• Two 12-bit ADCs with configurable 

resolution. Single or differential 

output mode operation for improved 

noise rejection. 500 ns conversion 

time achievable with programmable 

delay block triggering 

• Two 12-bit DACs for analog 

waveform generation for audio 

applications or sensor manipulation 

Memory 

• Dual Quad SPI supporting a double 

data rate interface, an enhanced 

read data buffering scheme, 

Execute-in-Place and support for 

dual-die flashes 

• Boot ROM with optional high 

assurance boot for secure booting 

capability 

• Up to 1.5 MB on-chip SRAM with 

ECC support on 512 KB 

8 


Vybrid V300 Block Diagram 

Debug and Trace 

JTAG 

Trace 

FlexTimer (8-ch.) 



IEEE ® Timers 

1588 Timers 

Periodic Interrupt Timers 

Low Power Timers 

Memory 

Boot ROM 

1 MB SRAM 

Memory Interfaces 

NAND Flash 

Controller 

Quad 

SPI x2 

External Bus 

Interface 

Performance 

System 

AMBA NIC 

Internal and 

External Watchdog 

Interrupt 

Router 

DMA 

Up to 64-ch. 

Power Management 

Regulators 

Memory Protection 

Unit 

• ARM Cortex-A5 core running at 266 

MHz, with double precision floating 

point, NEON media processing 

engine for acceleration of media and 

signal processing, and TrustZone 

security extensions. 32 KB each of 

instruction and data L1 cache and 

512 KB L2 cache for optimized 

bus bandwidth and on-chip SRAM 

execution performance 

• Up to 64-channel DMA for 

peripheral and memory servicing 

with reduced CPU loading and 

faster system throughput 

• Crossbar switch enables concurrent 

multi-master bus accesses, 

increasing bus bandwidth 

ARM ® Cortex-A5 

Up to 266 MHz 

Timing and Control 

• Three flex timers with a total of 12 

channels. Hardware dead-time 

insertion and quadrature decoding 

for motor control 

• Four-channel 32-bit periodic 

interrupt timer provides time base 

for RTOS task scheduler or trigger 

source for ADC conversion and 

programmable delay block 

HMI 

Core 

DP-FPU 

NEON 

L1 I/D-Cache 

L2 Cache 

Trace/Debug 

GIC 

Display Security 

TFT LCD 

Crypytography Module 

Segment LCD 

Touch Screen Controller 

Tamper Detect 

Secure RTC 

Video 

Video Interface w/Camera 

Secure RTIC 

Audio 

Secure RAM 

ASRC 

Secure Fuses 

SAI x3 

Secure WDOG 

ESAI 

Secure JTAG 

Analog 

12-bit ADC x2 

12-bit DAC x2 

PLL 

Clocks 

Clock 

Monitors 

Internal Reference 

Clocks 

Low/High Frequency 

Oscillators 

Communication 

UART x4 CAN x2 

DSPI x3 I 

IEEE 1588 

Ethernet x2 

L2 Switch 

USB OTG + PHY 

LS/FS/HS 

Secure Digital x1 

125 GPIO 

(with Interrupt) 

2C x2 

• TFT LCD display capable of 

WQVGA resolution 

• 288 segment LCD controller 

• Four-wire touch screen controller for 

resistive touch screens


• Xtrinsic low-power touch-sensing 

interface with up to 16 inputs. 

Operates in all low-power modes. 

Hardware implementation avoids 

software polling method. High 

sensitivity level allows use of overlay 

surfaces up to 5 mm thick 

Multimedia 

• Video interface unit with parallel 

camera support for 8- and 10-bit 

ITU656 video, up to 24-bit digital 

RGB 

• Three synchronous audio 

interfaces implementing fullduplex 

serial interfaces with frame 

synchronization such as I2S, AC97, 

and CODEC/DSP interfaces 

• Optional enhanced serial audio 

interface which provides a fullduplex 

serial port for communication 

with a variety of serial devices, 

including industry-standard codecs, 

SPDIF transceivers and other 

processors 

• Asynchronous sample rate converter 

for rate conversion between 32, 

44.1, 48 and 96 kHz 

Connectivity and 

Communications 

• USB 2.0 OTG controller with 

integrated PHY 

• 10/100 Ethernet controllers 

• Layer 2 Ethernet switch 

• Four UARTs with IrDA support 

including two UART with ISO7816 

smart card support. Variety of data 

size, format and transmission/ 

reception settings supported for 

multiple industrial communication 

protocols 

• Two CAN modules for industrial 

network bridging 

• Three DSPI and two I2C interfaces 


Reliability, Safety and 

Security 

• TrustZone Address Space Controllers 

provide memory protection for all 

masters on the crossbar switch, 

increasing software reliability 

• Cyclic redundancy check engine 

validates memory contents and 

communication data, increasing 

system reliability 

• Independent-clocked COP guards 

against clock skew or code runaway 

for fail-safe applications such as 

the IEC 60730 safety standard for 

household appliances 

• External watchdog monitor drives 

output pin to safe state external 

components if watchdog event 

occurs 

Optional Secure 

Application Support 

• Cryptography acceleration and 

assurance module 

Supports acceleration and 

off-loading for selected crypto 

algorithms such as AES, DES, 3 

DES, ArcFour Symmetric key blog 

ciphers 

• Random number generation 

NIST compliant SP800-90 

Combination of a true random 

number generator and a pseudorandom 

number generator 

• Real-time integrity checker 

Periodic check on system 

memory for unauthorized 

modifications 

• Secure non-volatile storage 

Secure non-rollover real-time 

counter 

Non-rollover monotonic counter 

Zeroizable 256-bit secret key 

• Tamper detection 

Support for up to six external 

tamper detection inputs 


External Peripheral Support 

• Secure digital host controller 

supports SD, SDIO, MMC or 

CE-ATA cards for in-application 


adding Wi-Fi ® support 

• NAND flash controller supports up 

to 32-bit ECC current and future 

NAND types. ECC management 

handled in hardware, minimizing 

software overhead 

• FlexBus external bus interface 

provides glueless interface options 

to memories and peripherals such 

as graphics displays. Supports up 

to four chip selects 

Tools and Software 

• Freescale Tower System hardware 

development environment 

• Integrated development 

environments 

Reference MQX BSP 

CodeWarrior V10.x (Eclipse) IDE 

with Processor Expert software 

ARM DS5 MDK 

Runtime software 

Math and encryption libraries 

Motor control libraries 

Lightweight media framework 

Complimentary bootloaders 

(USB, Ethernet, RF, serial) 

Complimentary Freescale 

embedded GUI software driver 

for graphics LCD panels 

Complimentary Freescale MQX 

Cost-effective Nano SSL/ 

Nano SSH for Freescale 

MQX RTOS 

• Full ARM ecosystem 

9



Single core solution with dual USB and integrated PHY 

for mobility and automation 

The VF4xx family features 

the ARM ® Cortex-A5 core 

with speeds up to 500 MHz 

with 512 KB L2 cache, dual 

USB 2.0 OTG controllers 

with integrated PHY, 1 MB 

of on-chip SRAM and a rich 





• Building automation 

• Gaming controllers 

• Point-of-sale 




output mode operation for 

improved noise rejection. 500 

ns conversion time achievable 

with programmable delay block 

triggering 




Memory 








capability 

• Up to 1 MB on-chip SRAM with 


10 


Faraday F400 Block Diagram 


JTAG 

Trace 

Timers 





IEEE ® 1588 Timers 



Memory 

Boot ROM 

1 MB SRAM 


DDR Controller 

NAND Flash Controller 

Quad SPI x2 

External Bus Interface 

• 16-bit DDR controller with PHY 

and ECC support capable of 

DDR3/LPDDR2 800 MHz data rate 

Performance 

System 

AMBA NIC 

Internal and 


Interrupt 

Router 

DMA 

Up to 64-ch. 


Regulators 


Unit 

TFT LCD 


Video 


Audio 

• ARM Cortex-A5 core with 

frequency up to 500 MHz, with 

double precision floating point, 

NEON media processing engine 

for acceleration of media and 


security extension. 32 KB each of 










Up to 500 MHz 

• Crossbar switch enables 

concurrent multi-master bus 

accesses, increasing bus 

bandwidth 


• Four flex timers with a total of 20 









HMI 

Core 

DP-FPU 

NEON 

L1 I/D-Cache 

L2 Cache 

Trace/Debug 

GIC 


ASRC 

SAI x4 

ESAI 


Tamper Detect 

Secure RTC 

Secure RTIC 

Secure RAM 

Secure Fuses 

Secure WDOG 

Secure JTAG 

Analog 

12-bit ADC x2 

12-bit DAC x2 

PLL 

Clocks 

Clock 

Monitors 


Clocks 


Oscillators 

Communication 


DSPI x4 I 2 C x4 

IEEE 1588 

Ethernet 

USB Host + PHY 

LS/FS/HS 

USB OTG + PHY 

LS/FS/HS 


141 GPIO 


• TFT LCD display capable of up to 

XGA resolution


• Four-wire touch screen controller 

for resistive touch screens 





software polling method. High 

sensitivity level allows use of 

overlay surfaces up to 5 mm thick 

Multimedia 




RGB 

• Up to four synchronous audio 



synchronization such as I 2 S, AC97, 


• Enhanced serial audio interface 

which provides a full-duplex serial 

port for serial communication with 

a variety of serial devices, including 

industry-standard codecs, SPDIF 

transceivers and other processors 

• Asynchronous sample rate 

converter for rate conversion 

between 32, 44.1, 48 and 96 kHz 



• Dual USB 2.0 OTG controller with 


• 10/100 Ethernet controller 

• Up to six UARTs, with IrDA support 

including two UARTs with ISO7816 





protocols 



• Four DSPI and four I 2 C interfaces 



Security 

• TrustZone Address Space 

Controllers provide memory 

protection for all masters on 

the crossbar switch, increasing 

software reliability 






against clock skew or code 

runaway for fail-safe applications 

such as IEC 60730 safety standard 

for household appliances 



components if watchdog event 

occurs 







algorithms such as AES, DES, 

3 DES, ArcFour Symmetric key 

blog ciphers 









modifications 



counter 





Support for up to 10 external 

passive tamper detection pins 

or five active external tamper 

detection pin pairs 





















environments 

Reference Linux BSP 




ARM DS5 MDK 



Media framework 

Complimentary bootloaders 

(USB, Ethernet, RF, serial) 


embedded GUI software driver 

for graphics LCD panels 



Nano SSH for Freescale MQX 

RTOS 


11

Vybrid Family 



Single core solution with dual Ethernet and L2 switch 

for automation and control 

The VF5xx family features 

the ARM ® Cortex-A5 core 

with speeds up to 500 MHz 

with 512 KB L2 cache, dual 

USB 2.0 OTG controllers 

with integrated PHY, dual 

10/100 Ethernet controllers 

with L2 switch, 1 MB of 





The VF5xx family is pin and 

software compatible with 

the VF4xx family. 


• Industrial control 

• Networked HVAC systems 

• Portable consumer devices 

• Networked audio system 











Memory 






12 


Faraday F500 Block Diagram 


JTAG 

Trace 

Timers 








Memory 

Boot ROM 

1 MB SRAM 




Quad SPI x2 




capability 



• 16-bit DDR controller with PHY and 

ECC support capable of DDR3/ 

LPDDR2 800 MHz data rate 

Performance 

System 

AMBA NIC 

Internal and 


Interrupt 

Router 

DMA 

Up to 64-ch. 


Regulators 


Unit 

• ARM Cortex-A5 core with 

frequency up to 500 MHz, with 

double precision floating point, 

NEON media processing engine 

for acceleration of media and 


security extension. 32 KB each of 





Core 


Up to 500 MHz 

DP-FPU 

NEON 

L1 I/D-Cache 

L2 Cache 

Trace/Debug 

GIC 


TFT LCD 



Tamper Detect 

Video 

Secure RTC 


OpenVG GPU 

Secure RTIC 

Audio 

Secure RAM 

ASRC 

Secure Fuses 

SAI x4 

ESAI 

Secure WDOG 

SPDIF 

Secure JTAG 









Analog 

12-bit ADC x2 

12-bit DAC x2 

PLL 

Clocks 

Clock 

Monitors 


Clocks 


Oscillators 

Communication 


DSPI x4 I 

IEEE 1588 

Ethernet x2 

L2Switch 


LS/FS/HS 

USB OTG + PHY 

LS/FS/HS 


141 GPIO 


2C x4 









programmable delay block

HMI 


• TFT LCD display capable of XGA 

resolution 


resistive touch screens 





software polling method 

• High sensitivity level allows use of 


Multimedia 



ITU656 video, up to 24-bit digital RGB 

• OpenVG GPU for UI acceleration 








serial port for serial 

communication with a variety 

of serial devices, including 


transceivers, and other processors 

• Sony Philips Digital Interface 

receives and transmits digital audio 

using the IEC60958 standard 

consumer format 

• Asynchronous sample rate 

converter for rate conversion 






• Dual 10/100 Ethernet controller 









protocols 



• Four DSPI and four I2C interfaces 


Security 
















components if watchdog event occurs 








DES, ArcFour Symmetric key blog 

ciphers 






• Real time integrity checker 



modifications 



counter 





























environments 





ARM DS5 MDK 




Complimentary bootloaders (USB, 

Ethernet, RF, serial) 


embedded GUI (eGUI) software 

driver for graphics LCD panels 




RTOS 


13

Vybrid Family 



Dual heterogeneous core solution with XGA display, dual USB, 

dual Ethernet and L2 switch for automation and HMI 

The VF6xx is the 

heterogeneous dualcore 

family combining the 

ARM ® Cortex-A5 and 

Cortex-M4 cores. 

It includes dual USB 2.0 OTG 

controllers with integrated 

PHY, dual 10/100 Ethernet 

controllers with L2 switch, 

1 MB of on-chip SRAM and a 

rich suite of communication, 




• Industrial automation 

• Health care systems 

• Multi-lane point-of-sale 

• Buildling control 











Memory 


data rate interface, an enhanced read 

data buffering scheme, Executein-Place 

and support for dual-die 

flashes 



capability 

14 




JTAG 

Trace 

Timers 








Memory 

Boot ROM 

1 MB SRAM 




Quad SPI x2 







Performance 

Core 


Up to 500 MHz 

DP-FPU 

NEON 

L1 I/D-Cache 

L2 Cache 

Trace/Debug 

GIC 

• ARM Cortex-A5 core with frequency 

up to 500 MHz, with 32 KB each 

instruction and data L1 cache 

and 512 KB L2 cache double 

precision floating point, NEON media 

processing engine for acceleration 

of media and signal processing, and 

TrustZone security extension 

• ARM Cortex-M4 core running 

up to 167 MHz, with 16 KB of 

instruction/data L1 cache plus 64 

KB of tightly coupled memory, 

DSP support for single cycle 

32-bit MAC, single instruction 

System 

AMBA NIC 

Internal and 


Interrupt 

Router 

DMA 

Up to 64-ch. 

Power 

Management 

Regulators 

Memory 

Protection 

Unit 

Core 

ARM ® Cortex-M4 

Up to 167 MHz 

SP-FPU 

DSP 

Trace/Debug 

I/D-Cache 

NVIC 


TFT LCD 



Tamper Detect 

Video 


Secure RTC 

OpenVG GPU 

Secure RTIC 

Audio 

Secure RAM 

ASRC 

Secure Fuses 

SAI x4 

ESAI 

Secure WDOG 

SPDIF 

Secure JTAG 

multiple data extensions and single 

precision floating point unit 









Analog 

12-bit ADC x2 

12-bit DAC x2 

PLL 

Clocks 

Clock 

Monitors 


Clocks 


Oscillators 

Communication 


DSPI x4 I 

IEEE 1588 

Ethernet x2 

L2Switch 


LS/FS/HS 

USB OTG + PHY 

LS/FS/HS 


141 GPIO 


2C x4 









programmable delay block

HMI 


• TFT LCD display capable of up to 

XGA resolution 



• Xtrinsic low power touch-sensing 


Operates in all low-power modes 

(minimum current adder when 

enabled). Hardware implementation 

avoids software polling method. 

High sensitivity level allows use of 


Multimedia 




RGB 













transceivers and other processors 





• Asynchronous Sample Rate 

Converter for rate conversion 






• Dual 10/100 Ethernet controller 





size, format and transmission/reception 


settings supported for multiple 

industrial communication protocols 





Security 
























DES, ArcFour Symmetric key 

blog ciphers 









modifications 



counter 





























environments 





ARM DS5 MDK 

IAR Embedded Workbench 

Runtime software and RTOS 










Cost-effective Nano SSL/Nano 

SSH for Freescale MQX RTOS 


15



Dual heterogeneous core solution with dual XGA display, 

GPU for portable systems 

The VF7xx dual 

heterogeneous core 

solution combines the 

ARM ® Cortex-A5 and 

Cortex-M4 cores. Features 

include dual TFT LCD 

support up to XGA resolution, 

dual USB 2.0 OTG controllers 

with integrated PHY, 10/100 

Ethernet controller, 1 MB of 






• Cost-sensitive gaming systems 

• Portable data terminals 

• Internet appliances 

• Mid-range white goods/appliances 











Memory 


data rate interface, an enhanced read 

data buffering scheme, Execute-in- 

Place and support for dual-die flashes 



capability 

16 




JTAG 

Trace 

Timers 








Memory 

Boot ROM 

1 MB SRAM 




Quad SPI x2 


• Up to 1 MB SRAM with ECC on 

512 KB 




Performance 

Core 


Up to 500 MHz 

DP-FPU 

NEON 

L1 I/D-Cache 

L2 Cache 

Trace/Debug 

GIC 

• ARM Cortex-A5 core with frequency 

up to 500 MHz, with 32 KB each 

instruction and data L1 cache 

and 512 KB L2 cache double 

precision floating point, NEON media 

processing engine for acceleration 

of media and signal processing, and 

TrustZone security extension 

• ARM Cortex-M4 core running up to 

167 MHz, with 16 KB of instruction/ 

data L1 cache plus 64 KB of tightly 

coupled memory, DSP support 

for single cycle 32-bit MAC, single 

instruction multiple data extensions 

and single precision floating point unit 

System 

AMBA NIC 

Internal and 


Interrupt 

Router 

DMA 

Up to 64-ch. 

Power 

Management 

Regulators 

Memory 

Protection 

Unit 


















HMI 

Core 


Up to 167 MHz 

SP-FPU 

DSP 

Trace/Debug 

I/D-Cache 

NVIC 


TFT LCD 


Video 


Tamper Detect 


Secure RTC 

Video ADC 

OpenVG GPU 

Secure RTIC 

Secure RAM 

Audio 

ASRC 

Secure Fuses 

SAI x4 

ESAI 

Secure WDOG 

SPDIF 

Secure JTAG 

Analog 

12-bit ADC x2 

12-bit DAC x2 

PLL 

Clocks 

Clock 

Monitors 


Clocks 


Oscillators 

Communication 


DSPI x4 I 2 C x4 

IEEE 1588 

Ethernet 


LS/FS/HS 

USB OTG + PHY 

LS/FS/HS 


141 GPIO 


• Dual TFT LCD display capable of up 

to XGA resolution




• Xtrinsic low power touch-sensing 


Operates in all low-power modes 

(minimum current adder when 

enabled). Hardware implementation 

avoids software polling method. 

High sensitivity level allows use of 


Multimedia 



ITU656 video, up to 18-bit digital RGB 













transceivers, and other processors 





• Asynchronous sample rate converter 

for rate conversion between 32, 

44.1, 48 and 96 kHz 





• 10/100 Ethernet controller 







protocols 






Security 



masters on the cross bar switch, 




















algorithms like AES, DES, 3 DES, 

ArcFour Symmetric key blog 

ciphers 









modifications 



counter 





passive tamper detection pins or 

up to five active external tamper 























environments 





ARM DS5 MDK 


Runtime software and RTOS 

Math, DSP and encryption 

libraries 











RTOS 


17

Technical Highlights

Core Technology 

ARM ® Cortex-A5 and ARM Cortex-M4 processors 

In developing a new generation, 40 nm 

integrated 32-bit family, Freescale 

defined a dual-core architecture, 

combining the best features of the 

industry-standard ARM ® Cortex-A5 

application processor with the realtime 

focus of an ARM Cortex-M4 

control processor. Indeed, the 32-bit 

Vybrid family provides rich application 

capabilities with real-time control 

because each core has unique 


attributes that make it the appropriate 

choice for specific embedded 

application spaces. The Vybrid family 

is ideally suited for automotive, 

industrial and general embedded 

applications. This solution is highly 

integrated, reducing system cost for 

the target applications. It includes 

a number of advanced architectural 

features so it can support either MCU 

or MPU configurations. 

Vybrid Processor Cores and Slave Memories Block Diagram 

Tag 7 

(Optional) 

Tag 0 

0 

1 

Data 

7 

RAM 

Array, 32K 

Tag/Data 

Arrays, 2x 8K 

The processor architecture can also 

be configured as a uniprocessor with 

either the ARM Cortex-A5 or the ARM 

Cortex-M4 as the operating core. 

For markets needing a single-core 

applications processor in the ARM 

Cortex family, the ARM Cortex-A5 is 

the best “value” application processor 

(in terms of MIPS/mW). Other key 

device components include a large 

ARM 

TPIU 

CTI 

DAP 

® Cortex-A5 Core Complex ARM ® Cortex Core Complex 

Debug (ITM, ETM, ETB, CTI) 

FPU + NEON 

NVIC FPU 

CM4 CPU 

FPB 

DWT 

Mul 

Inst 

ALU/Shift Q 

Ld/St 

PFU and Branch Predictor 

AP Bus Matrix ITM 

SystemBus CodeBus 

Data uTLB Inst uTLB 

TCMU 

TCML 

STB 

D-$ 

TLB 

4 x 8K 

AXI BIU 

L2 Cache Controller 

AXI System Bus 

64 

DDRC Quad SPI 

I-$ 

2 x 16K 

OCRAM 

_sys 

NIC-301 

OCRAM 

_sys 

OCRAM 

_gfx 

Boot 

ROM 

Sys-$ 

AHB System Bus 

Sys 

BIU 

Code 

BIU 

FlexBus PBRIDGE 

Code-$ 


RAM 

Array, 32K 

Tag/Data 

Arrays, 2x 8K 

64 64 

64 

AHS Code Bus AHB Backdoor Port 

19


on-chip RAM, display controller units, 

OpenVG graphics processing unit, 

Quad SPI interfaces to external flash 

memories and available RTOS. All 

these components combine to provide 

a low system cost BOM because 

DRAM is not required. 

Target applications for single-core ARM 

Cortex-M4/Cortex-A5 MPU devices in 

the multi-market, general embedded 

space include asset tracking devices, 

2D scanners, point-of-sale terminals, 

networked audio and data acquisition. 

In the industrial space, a single-core 

ARM Cortex-A5 MPU is targeted at 

industrial control, gas pumps and 

building control applications. Medical 

applications include patient monitoring 

and drug delivery mechanisms. 

A common theme in developing 

a dual-core architecture for these 

market segments is the inherent issues 

associated with a high-performance 

single (applications) processor running 

a high-level operating system coupled 

with the need for good real-time 

control. Vybrid devices address this 

growing number of consumer and 

industrial embedded applications that 

need higher application performance 

plus real-time responsiveness with its 

dual-core architecture combining the 

ARM Cortex-A5 application processor 

and the ARM Cortex-M4 for real-time 

control. 

This approach offers considerable 

flexibility in partitioning the software 

architecture across the dual-core 

hardware resources and provides 

options for reducing the RunIDD 

current consumption. It also removes 

the need for system designers to 

specify a higher performance single 

processor device in an effort to 

“oversample” the real-time events, 

thereby reducing system cost and 

power dissipation. 

20 

Vybrid Core Architecture Summary Comparison 

A “processor-centric” high-level 

Vybrid device block diagram is 

presented in the previous figure. The 

basic microarchitecture includes 

the dual-core structure interfacing 

to the network interconnect system 

bus fabric, providing the hardware 

interconnect matrix and supporting a 

64-bit third-generation ARM-AMBA 

Advanced eXtensible Interface split 

transaction protocol. This is followed 


Vybrid Key 

Architecture Features ARM ® Cortex-A5 ARM Cortex-M4 

Instruction set architecture ARMv7-A ARMv7-ME, +-M4F (FPU) 

Architecture width 32 bits 32 bits 

Operating frequency 

relative to platform 

(2,3) x platform MHz 1x platform MHz 

Integer performance 

Microarchitecture 

1.57 DMIPS 2.1 per MHz 1.25 DMIPS 2.1 per MHz 

• Pipeline 

Eight stages 

Three stages 

• Instruction issue 

Limited superscalar (ALU + Br) Single 

• Execution units 

L1 processor, local memories 

• Capacity, organization 

VFPv3 (SP + DP FPU) 

NEON SIMD 

MMU, TrustZone 

I-Cache, D-Cache 

I-Cache = 32 KB, 

2-way SA 

D-Cache = 32 KB, 

4-way SA 

32 byte cache line size 

(4 beat, 64-bit burst) 

SPFPU 

v7-ME (DSP + SIMD) 

CodeCache, SystemCache, 

TCM (Lower, Upper) 

CodeCache = 16 KB, 

2-way SA 

SystemCache = 32 KB, 

2-way SA 

32 byte cache line size 


TCML(ower) = 32 KB 

TCMU(pper) = 32 KB 

Accesses from other 

masters via backdoor port 

L2 processor memories Optional L2 Cache 

• Capacity, organization L2-Cache = 512 KB, 

8-way SA 

32 byte cache line size, 


System bus interface 1x 64-bit AMBA3 AXI 2x 64-bit AMBA2 AHB-Lite 

On-chip RAM (OCRAM) Three 64-bit AXI ported memory controllers + arrays, 1.5 MB total 

• 2x system RAM (_sys) controllers, each 256 KB in capacity, 

512 KB total 

Optionally includes single-bit correction, double-bit detection 

(SECDED) ECC 

• 1x Graphics RAM (_gfx) Controller, 1 MB total 

512 Kbytes optionally used as L2 cache data array 

Programmable support for on-the-fly conversion of 16-bit 

pixel data to/from 32-bit ARGB8888 

DDR DRAM controller 2x 64-bit AXI input ports and 16-bit external DDR data bus 

Quad SPI memory controller 2x Quad SPI external memory controller 

FlexBus memory controller 

Gluelessly interfaces to external (non-DRAM) memories and/or 

ASICs, six chip selects 

by connections to a full complement of 

on-chip memories and slave peripherals 

connected via peripheral bridges as 

well as memory controllers for external 

interfaces including a multi-ported 

DDR DRAM controller, dual Quad SPIs 

and a FlexBus controller for glueless 

interfaces to simple (non-DRAM) 

memories and/or ASIC devices.


ARM ® Cortex-A5 Processor Pipeline Organization 1 

Fetch 1 Fetch 2 Fetch 3 

ARM ® Cortex-M3 and ARM Cortex-M4 Pipeline 

For the standard configuration, Vybrid 

systems can best be characterized as 

a heterogeneous, symmetric, cachebased 

dual-core MPU architecture. 

The two ARM Cortex cores share 

an instruction set architecture with 

a common memory map, and the 


Instruction ruc 

Queue ue 

Decode 

1 “ARM’s Midsize Multiprocessor, Next Cortex-A5 Supports 

Four-Way Coherent Multiprocessing,” Tom R. Halfhill, 

Microprocessor Report, 10/26/2009 

LSU branch 

result 

Fe De Ex 

Fetch 

Address 

Generation 

Unit 

Instruction 

Decode 

and 

Register 

Read 

Branch 

Address 

Phase 

and 

Writeback 

Shift 

Multiply 

and 

Divide 

Branch Forwarding 

and Speculation 

LU Branch No Forwarded/Speculated 

Issue 

Addr 

Gen 

Data 

Phase 

Load/ 

Store 

and 

Branch 

ALU 

and 

Branch 

LSU Branch Result 

Mul1 

Shift 

Delta 

Cache 

1 

FP1 

address space is effectively accessible 

from either core. Memory coherency is 

wholly managed by software. There is 

hardware support for basic multicore 

requirements including peripheral 

interrupt steering plus directed 

CPU interrupts for inter-processor 


WR 

Mul2 

ALU 

Delta 

Cache 

2 

FP2 

Writeback 

Writeback 

Writeback 

FP3 FP4 FP5 

communication, semaphores, run/ 

halt/reset control, memory protection 

via ARM’s TrustZone architecture with 

Freescale security extensions and 

shared dual-core debug resources 

including cross-triggering capabilities. 

With significant amounts of both 

processor-local memories (L1 core 

caches, ARM Cortex-M4’s tightly 

coupled memories with its backdoor 

port for alternate bus master 

accesses, and the optional ARM 

Cortex-A5 512 KB L2 cache) and 

the SoC resources associated with 

on-chip RAM and boot ROM plus 

the controllers for the external DDR 

DRAM, Quad SPI (flash) memories 

and FlexBus, the Vybrid architecture 

is a high-performance dual-core 

implementation, providing rich 

applications in real time for a number 

of growing embedded application 

spaces. 

21


Multicore Communication 

A flexible API for communicating between 

heterogeneous cores 

A multicore architecture brings new 

challenges to system design because 

the software must be rewritten to 

distribute tasks across the available 

cores. In addition, all the peripheral 

resources need to be properly 

allocated to avoid resource contention 

and share the data spaces between 

the cores efficiently. 

The Vybrid multicore solution with 

heterogeneous cores anticipates a 

customer running a high-level OS such 

as Linux on the ARM ® Cortex-A5 

and an RTOS such as Freescale’s 

MQX on the ARM Cortex-M4. 

Because of its real-time nature, the 

RTOS has a priority-based preemptive 

scheduler that is the heart of its 

task management services. These 

services could be communication and 

synchronization among tasks running 

on the same processor including 

messaging, semaphores, mutexes 

and event flags. A multicore SoC 

also needs mechanisms for reliable 

communication and synchronization 

among tasks running on different 

processing cores. 

22 

Multicore Communications Architecture 


(Linux ® ) 

IPC API 

Transport Layer 

OS Specific Driver 

The Solution: Multicore 

Communication 

Data Path 

Freescale’s solution to the multicore 

architecture with different OSs is 

a multicore communication (MCC) 

protocol that takes maximum 

advantage of heterogeneous 

asymmetric multiprocessing (AMP) 

SoCs. It includes an easy-to-use API 

that can be easily extended to support 

additional operating systems and 

features. 

The MCC protocol is designed for low 

latency and low overhead operation 

and is optimized for embedded 

environments with constrained CPU 

and memory resources. To achieve this, 

the protocol is exclusively implemented 

using shared memory with no data 

translation or message headers. 

Data Path 

Shared Memory 


(MQX) 

IPC API 

Transport Layer 

OS Specific Driver 


Multicore, multi-OS architecture provides shared memory and message-based communication paths. 

Applications communicate using a 

client-server methodology. To do this, 

each application participating on the 

separate OS creates a connection 

to a specific protocol port with one 

endpoint receiving data and the 

other sending data. In addition, each 

endpoint has its own associated 

port for each channel, similar to BSD 

sockets. To simplify the design, all 

communication is message-based and 

avoids connection-oriented or packetbased 

data streams. Messages can 

be queued on the receive end up to a 

configurable limit. 

As shown in the figure above, 

messages pass between endpoints 

via bidirectional connection-less 

communication channels.


A tuple (node, port) uniquely identifies 

each endpoint. In addition, each 

independent thread of execution 

with a private memory space can 

operate as a node. This implies that 

a single-process RTOS like MQX will 

have, at most, one node. In contrast, 

a multi-process OS like Linux ® could 

contain one node per process. A port 

operates as a mailbox location where 

data can be delivered. Each node can 

utilize multiple ports and the same 

port can be used simultaneously by 

multiple nodes. 

Implemented as a user space library, 

the protocol includes an external 

API and transport layer. Supported 

operating systems include kernel 

components that allow the protocol to 

take advantage of Freescale hardware 

architecture features to synchronize 

shared memory access. 

Hardware Architecture 

The new heterogeneous AMP SoC 

includes several hardware features 

that allow optimal implementation of 

the MCC. 

The shared memory region used by 

all cores has two distinct areas: one 

for configuration and bookkeeping, 

and the other for data buffers. 

Hardware semaphores are used 

as the synchronization primitive to 

surround critical sections of code that 

access shared memory blocks. The 

hardware semaphore synchronization 

is required since each core is 

separately running an instance (or 

instances) of the MCC library. 


CPU-to-CPU interrupts signal when 

new blocks are available for data 

sending and when data exists 

to be received. This mechanism 

implements the blocking versions of 

the message-send and messagereceive 

API calls. 

MCC Advantages 

The MCC solution utilizes shared 

memory as the data transport 

mechanism. This design minimizes 

communication latency by using 

zero-copy, so data passes by 

reference rather than physically 

being copied. 

A good example of where this low 

latency can provide significant 

application benefits is in network 

processing. With network processing, 

data transmission occurs frequently 

and in large quantities based on 

the high-bandwidth network traffic 

that Ethernet and proprietary 

communication protocols can deliver. 

MCC with zero-copy can off-load 

the network processing. In a typical 

application, the ARM Cortex-M4 core 

receives and processes complex 

network data and feeds the raw data 

back to the ARM Cortex-A5 core for 

use by an application. 


Additional use cases that can take 

advantage of the Vybrid device 

capabilities include: 

• Segmenting real-time application 

code. This involves running realtime 

code on the ARM Cortex-M4 

core to operate independently of 

higher-latency code running on 

the ARM Cortex-A5 core. The new 

MCC can be used to share data 

between them 

• Off-loading CPU-intensive 

operations. An audio software 

platform may experiment with 

executing audio stream parsing and 

decoding on the ARM Cortex-M4 

core to improve the real-time 

responsiveness of the UI and other 

applications running on the ARM 

Cortex-A5 

• Minimizing power draw. The 

ARM Cortex-M4 core can be 

the primary component of the 

system during periods of low 

CPU utilization/idling and the 

ARM Cortex-A5 can be activated 

during periods of high-demand or 

for specific CPU-intensive tasks. 

This synchronization would be 

accomplished using Freescale MCC 

• Partitioning sensitive code for 

medical or safety reasons 

23


Multimedia Subsystem 

Enabling rich apps with hardware acceleration 

The Vybrid multimedia subsystem 

consists of the video interface unit 

(VIU), display control unit, touch screen 

controller, segment LCD, OpenVG 

GPU and the audio subsystem. 

This multimedia subsystem helps 

to minimize and possibly eliminate 

the need for the cores to handle 

any pixels, allowing them to manage 

system level tasks. 

24 

Multimedia Block Diagram 

Display 

TFT LCD 


Segment LCD 

Video 

Video Camera Interface 

Open VG GPU 

Audio 

ASRC 

SAI x 4 

ESAI 

SPDIF 

This section will describe the more 

complex IP in the multimedia 

subsystem and give a pictorial 

representation of the pixel processing 

of the subsystem. 

Video Subsystem 

VIU 

The VIU provides a 24-bit parallel 

interface for digital video. The VIU 

accepts ITU-R BT.565-compatible 

video, digital RGB and YUV444 

formats on its parallel interface, 

decodes it and optionally performs 

processes such as down-scaling, 

horizontal up-scaling, brightness 

and contrast adjustment, YUV to 

RGB conversion, deinterlacing and 

Multimedia Pixel Processing 

Digital 

Input 

Camera 

Image Signal 

Image Processing 

and Scaling 

Combining with Audio 

Audio Compression 


horizontal mirroring. The resulting 

video stream is stored to system 

memory for subsequent postprocessing 

and displayed by a display 

control unit. 

The video subsystem supports both 

digital and analog inputs. In the case 

of digital video, the interface is directly 

into the VIU module either as RGB 

data or an ITU-R BT-565 compatible 

YUV data stream. For composite video 

the on-chip video analog decoder 

(video ADC) is required, the output of 

which will feed the VIU digital input. 

The input formats supported for 

composite video are PAL and NTSC 

and up to four input channels are 

muxed down to one ADC. 

Image Sensor Display 

Analog 

Input 

Video ADC 

Video Interface Unit (VIU) 

System Memory 

Memory 

Communication Network 

ARM 

Display Control Unit 

(DCU) 

RLE Decompression 

of Compressed Image 

in Memory 

Run Length Encoder (RLE) 

Lossless Decompression 

Separation from Audio 

Audio Decompression 

Display Enhancement 

Video/Graphics Combining 

Graphics 

Acceleration 

Rotation 

ColorSpace 

Conversion 

Graphic Processing Unit 

(GPU) 

Hardware Accelerated


OpenVG GPU Subsystem Block Diagram 

AHB 

Features 

• Supports QVGA to XGA 

• Input options: 

8/10-bit ITU656 video 

Up to 24-bit digital RGB 

• Scaling: 

Command 

System 

Up to 1/8 video down-scaling with 

different scaling ratios in horizontal 

and vertical directions 

Up to 2x video up-scaling in 

horizontal direction 

• Brightness and contrast adjustment 

• YUV to RGB888 or RGB565 

conversion 

• De-interlace function 

OpenVG GPU 

The vector graphics processing is 

based on the Vivante GC355 core 

supporting the OpenVG1.1 API. Using 

a vector graphics core, Vybrid devices 

support applications that require flash 

acceleration or UI acceleration. 

Features 

• Real-time hardware curve 

tesselation of lines, quadratic and 

cubic Bezier curves 

• 16x line anti-aliasing 

• OpenVG 1.1 support 

• Vector drawing 


Vector Graphics 

Pipeline 

Tessellation 

Engine 

GC355 

Texture + 

Gradient 

Unit and 

Cache 

Pixel 

Backend 

MMU 

System 

Interface 

Display Subsystem 

Display Controller Unit 

The display controller unit (DCU) is 

the interface to TFT LCD displays. 

It generates all the signals required 

to drive the display. Layer data is 

stored in on-chip or external memory 

and is fetched by the internal DMA 

channels of the DCU. The layer 

data is described using layer control 

descriptors that form part of the 

register set of the DCU. 

Features 

• Resolutions supporting up to XGA 

(1024x768) 

• Generates full RGB888 data and 

control signals for TFT display 

• Direct blitting engine with real time 

alpha-blending 

• Blending of each pixel using up to 

six source layers 

• Total of 64 graphics layers 

• Gamma correction with 8-bit 

resolution on each color component 

• Temporal dithering 

• Window feature allowing easy 

cropping and horizontal scrolling 

with low CPU overhead 


AXI 

Audio Subsystem 

The audio subsystem has IP to 

provide options for everything from 

asynchronous sample rate conversion 

to a stereo transceiver that can receive 

and transmit digital audio. 

Synchronous Audio Interface 

Synchronous audio interfaces (SAI) 

are used to transfer audio data. 

The SAI supports full-duplex serial 

interfaces with frame synchronization 

such as I 2 S, AC97 and CODEC/ DSP 

interfaces. 

Features 

• Transmitter with independent bit 

clock and frame sync supporting 

one data line 

• Receiver with independent bit clock 

and frame sync supporting one data 

line 

• Word size programmable from 8- to 

32-bit 

• Asynchronous 64/32 x 32-bit FIFO 

for each transmit and receive data 

line 

25


Enhanced Serial Audio Interface 

The enhanced serial audio interface 

(ESAI) provides a full-duplex serial 

port for communication with a variety 

of serial devices including industrystandard 

codecs, SPDIF transceivers, 

and other processors. The ESAI 

consists of independent transmitter 

and receiver sections, each section 

with its own clock generator. 

Sony/Philips Digital Interface 

The Sony/Philips Digital Interface 

module is a stereo transceiver that 

allows the processor to receive and 

transmit digital audio over it using 

the IEC60958 standard, consumer 

format. 

Features 

• SPDIF receiver 

Input sample rate measurement 

Supports the following sampling 

rates: 32, 44.1, 48, 64, 88.2 and 

96 kHz 

CD text support 

CS and U bit recovery 

• SPDIF transmitter 

One SPDIF output, IEC 60958 


CS bit support 

• Low-power mode 

SPDIF can be disabled to save 

power when not in use 

26 

Audio Subsystem Block Diagram 

ASRC 

External 

(Virtual) Clocks 

SAI3 

SPDIF 

Asynchronous Sample Rate 

Converter 

The incoming audio data may be 

received from various sources at 

different sampling rates. The outgoing 

audio data may have different 

sampling rates and it can also be 

associated to output clocks that are 

asynchronous to the input clocks. The 

asynchronous sample rate converter 

(ASRC) converts the sampling rate of 

a signal associated with an input clock 

into a signal associated to a different 

output clock. The ASRC supports 

concurrent sample rate conversion of 

up to 10 channels of about -120 dB 

THD+N. 

SAI2 SAI1 SAI0 

ESAI_FIFO 

ESAI 


Legend 

Data/Control 

Audio I/F 

Audio Clocks 

Dedicated 

Audio 

Modules 

Features 

• Supports up to 10 channels split 

into up to three sampling rate 

conversion sets 

• Individual association of each 

channel to one of the sampling rate 

pairs 

• Designed for rate conversion 

between 32, 44.1, 48 and 96 kHz. 

The useful audio signal bandwidth is 

below 24 kHz 

• Other sampling rates in the range 

of 8 to 200 kHz are also supported, 

but with reduced audio performance 

• Automatic accommodation to slow 

variations in the incoming and 

outgoing sampling rates 

• ASRC has a disable mechanism to 

save power when not in use


Security Subsystem 

Secure your applications in an insecure world 

Security is an increasingly 

important feature for industrial 

and consumer applications as the 

number of hacking incidents that 

expose sensitive information and 

unauthorized use of copyrighted 

content is on the rise. Helping to 

ensure secure applications is a 

high priority for the Vybrid platform. 

Sensitive information and digital rights 

management data can be stored in a 

protected manner and used, allowing 

e-commerce and advanced contentbased 

subscriber services. 

Security Block Diagram 

Security 


(CAAM) 

Tamper Detect 

Secure RTC 

Real-Time Integrity 

Checker (RTIC) 

Secure RAM 

Secure Fuses 

Secure WDOG 

Secure JTAG 


Security Subsystem: 

A Trusted Platform 

The foundation of a secure system 

consists of the hardware platform 

and the critical code that executes on 

that platform. This foundation is built 

with an on-chip ROM-based boot-up 

process that initiates validation of the 

platform, including the following tasks: 

• Examining key hardware elements 

to help ensure that they are 

functioning properly 

• Verifying the authenticity and 

integrity of the critical code that 

controls the overall operation of 

the system 

The boot process gains control of 

the system immediately after reset 

by executing known boot code that 

is resident in the on-chip ROM. After 

verifying the authenticity of a start-up 

script residing in external memory (i.e., 

NOR or NAND flash) the boot process 

follows that script using established 

cryptographic techniques to validate 

the authenticity and integrity of the 

operating system code and data in 

external memory. 


More flexibility is achieved by using 

electrically programmable fuses to 

enable or disable particular system 

functions. For example, it is possible 

to configure a production version, 

security-enabled device so that 

the JTAG debug port is completely 

disabled. For early prototype devices, 

portions of the security system can be 

selectively disabled, allowing access 

to otherwise inaccessible areas of the 

device. Full flexibility between these 

two extremes is possible. 

Software that is security aware is 

imperative for those products that 

need security. Sensitive data in 

plaintext form must not appear on 

external data buses, and it should be 

restricted to the minimum number of 

data paths internal to the chip. 

High Assurance Boot 

The high assurance boot (HAB) feature 

in the system boot ROM protects the 

platform from executing unauthorized 

software (malware) during the boot 

sequence. Unauthorized software can 

enter the platform during upgrades or 

re-provisioning or when booting from 

USB/UART connections or removable 

devices. If permitted to gain control 

of the boot sequence, unauthorized 

software can be the attack vector for 

a variety of goals including exposing 

stored secrets, circumventing access 

controls to sensitive data, services or 

networks and re-purposing the 

27


platform. HAB supports booting the 

device to a known initial state by 

using digital signatures to recognize 

authentic software and running 

software signed by the device 

manufacturer. 

In addition, HAB can protect the 

confidentiality of software during 

off-chip storage by decrypting the 

software loaded into RAM prior 

to execution. The figure to the 

right shows HAB encrypted boot 

supported on the Vybrid platform. 

The software image is encrypted 

using a secret key before being 

programmed on the off-chip memory 

(typically flash). During boot, HAB 

uses the same secret key (stored 

in hardware fuses not visible to the 

user) to decrypt the software image. 

Hardware Security 

Elements 

Vybrid platform security architecture 

includes the following hardware 

components: 





algorithms 

Supports NIST SP800-90 

compliant hardware random 


16K secure memory (automatic 

zeroization) with up to four 

independent partitions 

Supports AES, DES, 3 DES, 

ArcFour Symmetric key blog 

ciphers 

Supports MD5, SHA-1, SHA-224, 

SHA-256 hashing algorithms 




number generator and a 

pseudo-random number 

generator 

28 

Encrypted High Assurance Boot 

Encryption Using 

Secret Key 

SW Image 

Encrypt 

(AES) 

Encrypted 

SW Image 

Build Environment Device Boot 

Secret Key 

Manufacturing 

OTP Key 

CAAM (AES) 




modifications 

Supports up to four memory 

regions 

Use SHA-1 or SHA-256 as 

hashing algorithm 

Once started, RTIC can only be 

stopped and restarted by trusted 

software 



counter 



Support for tampers 

• Tamper Detection 

Support for up to six external 

tamper detectors 

Active tamper detection 

Wire mesh tamper 

Voltage, temperature and clock 

tamper detectors 

Key Blob 

Flash 

OTP Key 


Secret Key 

Decrypt 

(AES) 

Key Blob 

Decryption Using 

Secret Key 

Decrypted 

SW Image 

Decrypt 

(AES) 

Encrypted 

SW Image 

• TrustZone Address Space Controller 

Supports 2, 4, 8 or 16 

independent address regions 

Access controls are 

independently programmable for 

each address region 

Protects all AXI slave 

memories—DDR, on-chip SRAM 

All AHB slave memories, 

FlexBus, Quad SPI are protected 

by AHB equivalent address 

space controller 

• Other security sub-blocks 

Secure fuses (OTPs) 

Central security unit 

AHB TrustZone Controller 

Trust Zone Watchdog 

Secure JTAG Controller



Programmable power options for performance 

and long battery life 

The Vybrid platform was designed with 

power efficiency as one of its main 

goals. To reduce current consumption, 

the design has: 

• Dynamic power management of 

core and peripherals 

• Software-controlled clock gating of 

peripherals 

• Multiple power domains and voltage 

scaling to minimize leakage in lowpower 

modes 

Vybrid devices have a power 

management unit supporting a variety 

of operating modes to optimize SoC/ 

application power consumption. 

There are nine modes of operation 

to allow the user to optimize 

power consumption for the level of 

functionality needed as well as several 

wakeup sources for the power modes. 

A low-leakage wakeup unit has up 

to eight internal peripheral wake-up 

sources, as well as up to sixteen 

external pins for wakeups. Several 

wakeup sources are available in the 

lowest power mode: low-power timer, 

real-time clock, ADC, DAC and several 

pin interrupts. Depending on the 

requirements of the user application, a 

variety of stop modes are available that 

provide state retention, partial power 

down and/or full power down of certain 

logic and/or memory. I/O states are 

held in all modes of operation except 

power gated modes (LPSTOP1, 

LPSTOP2, LPSTOP3). I/O state for 

16 wakeup pads is still retained in 

power gated modes. 


Modes of Operation 

Modes General Description 

General Description Normal Normal Recovery Recovery Method 

Method 

RUN 

RUN 

All functionality of Faraday is available 

All functionality of Vybrid platform is available N/A 

N/A 

WAIT CA5 and CA5 CM4 and cores CM4 Halted cores halted Interrupt Interrupt 

LPRUN 24MHz 24 operation, MHz operation, PLL Bypass PLL bypass Interrupt Interrupt 

ULPRUN 

ULPRUN 

STOP 

STOP 

LPSTOP3 

32/128 kHz operation, PLL off Interrupt 

32kHz /128kHz operation, PLL Off Interrupt 

Lowest power mode with all power retained, 

Lowest power mode with all power retained, RAM 

Interrupt 

RAM retention and LVD protection 

Interrupt 

retention and LVD protection 

64K RAM retention. I/O states held. 

64K (tbd) 

ADCs/DACs 

RAM retention. 

optionally 

I/O states held. ADCs/DACs 

Wake-up/Reset 

FPO power-gated. RTC Wakeup/Reset 

optionally power-gated. RTC functional. Wakeup from 

interrupts functional. Wakeup from interrupts 

LPSTOP2 

LPSTOP2 

16K RAM retention. I/O states held. 

16K (tbd) RAM retention. I/O states held. ADCs/DACs 

optionally ADCs/DACs power-gated. optionally RTC functional. power-gated. Wakeup from RTC 

interrupts functional. Wakeup from interrupts 

Wake-up/Reset 

Wakeup/Reset 

LPSTOP1 I/O states I/O states held. ADCs/DACs held. ADCs/DACs optionally powergated. optionally RTC 

Wake-up/Reset 

LPSTOP1 functional. powergated. Wakeup from RTC interrupts functional. Wakeup from Wakeup/Reset 

Battery All supplies interrupts OFF, SRTC, 32kXOSC ON, tampers and monitors 

POR 

Backup ON. All supplies OFF, SRTC, 32k XOSC ON, 

Battery Backup 

tampers and monitors ON. 

POR 

LPRUN and ULPRUN are part of RUN Mode and there are no separate modes. 

Features 

• Single 3.3V+/-10% supply voltage 

• High-power voltage regulator 

with an external ballast transistor 

generating internal 1.2V supply 

voltage, 1.2A capacity and 

quiescent current less than 1 mA 

• Ability to switch supply voltage 

down from 1.2 to 1.1V in lowpower 

modes to minimize power 

consumption 

• Soft start of main high-power 

regulator to minimize in-rush 

currents. Start-up time < 500 us 

• Low-power regulator: For Stop 

modes. 50 mA capacity and 

quiescent current < 50 uA 


• Ultra-low power regulator: For 

LPStop modes. 10 mA capacity and 

quiescent current < 5 uA 

• Well bias generator to increase well 

by ~300mV to minimize leakage in 

low-power modes 

• Multiple power domains and power 

gating to minimize low-power 

consumption 

• Low voltage detection (LVD) on main 

supplies and 1.2V supplies 

• 16 wakeup pins for low-power 

wakeup 

• The single 3.3V supply is used in 

the system for I/O power with the 

exception of the DRAM interface. 

The DRAM interface power will 

be generated external to the 

Vybrid SoC 

29


Power Domains 

The Vybrid SoC is divided into six 

power domains: PD 4:0 and Vbat. 

• PD4: Main power domain. Contains 

full platform, cores, peripherals, 

clocking, PLLs and main 24 MHz 

XOSC. This domain is power 

gated off during LPSTOP modes 

of operation to minimize leakage 

power 

• PD3: ADC-DAC domain: This 

domain can be optionally powered 

off in LPSTOP modes depending 

if powered, ADC and DAC 

conversions can be performed in 

LPSTOP modes 

• PD2: 48 KB SRAM power domain: 

This domain can be optionally 

powered off in LPSTOP modes 

depending on the amount of SRAM 

that needs to be maintained 

• PD1: 16 KB SRAM power domain: 

This domain can be optionally 

powered off in LPSTOP modes if no 

SRAM retention is required 

• PD0: Always-on logic domain: This 

domain is always powered on in 

LPSTOP modes. It has wakeup 

logic, 24 MIRC, 128 KHz IRC and 

the voltage regulators 

• VBat: Battery/RTC domain: Contains 

the SecureRTC, 32 kHz XOSC, 

tamper and monitors. Powered by 

a coin cell when the main power 

supply is switched off 

30 

PMU Block Diagrams 

3.3V 

LVDs 

POR 

Regulator 

Coin Cell 

HPreg 

1.2V 

External ballast 

LPreg 

1.2V 

Internal ballast 

ULPreg 

1.2V 

Internal ballast 

2.5V LDO I/O and Analog 

1.1V LDO Analog 

3.3V LDO 

1.1V LDO 


Main Power Domain: 

Core, platform, memories, 

graphics, peripherals, 

clocks, PLLs 

ADC/DAC Domain: 

2x DAC, 2X ADC 

SRAM Domain1: 

48k SRAM 

SRAM Domain0: 

16k SRAM(tbc) 

Always-on Domain: 

Wakeup LPTim 

Battery Domain: 

SRTC, 32 kHz, 

Tampers, monitors 

PD4 

PD3 

PD2 

PD1 

PD0


Ethernet Subsystem 

Real-time networked measurement and control 

Vybrid devices, depending on the 

particular family, have dual Ethernet 

controllers and an L2 switch. The 

dual Ethernet controller modules, in 

conjunction with an external Ethernet 

PHY, are used to add Ethernet 

connectivity. Hardware IEEE ® 1588 

time stamping provides precision 

clock synchronization for real-time 

control in networked automation, test 

and measurement applications. Midto 

high-end industrial applications 

typically use dual Ethernet controllers. 

One Ethernet MAC can be used to 

manage the control nodes while the 

other Ethernet MAC can be used to 

connect to a remote sever for control 

or for redundancy. Most industrial 

Ethernet options (i.e., Profinet IRT or 


Application I/F Application I/F 


uDMA 

+ AHB I/F 

uDMA 

+ AHB I/F 

3 

0 

Profinet IRT+) require determinism, 

where IEEE 1588 is the enabling 

feature. Dual Ethernet with the L2 

switch allows daisy chaining which 

would otherwise need an expensive 

external switch. The function of the L2 

switch is to route packets from one 

Ethernet port to the other Ethernet 

port without any CPU intervention. 


Features 

• Dual 10/100 Ethernet MAC (MAC- 

NET) 

Hardware support for IEEE 1588 

standard for a precision clock 

synchronization protocol for 

networked measurement and 

control systems 

L2 Switch 

2 

1 

Receive 

FIFO 

Transmit 

FIFO 


Ethernet MAC 

TOE Functions 

TCP/IP 

Performance 

Optimization 

TCP/IP 

Performance 

Optimization 

Reduced media independent 

interface (RMII) support 

Interfaces with unified DMA 

Supports wakeup from lowpower 

mode through magic 

packets 

Multiple clock source options for 

time-stamping clock 

• L2 Ethernet switch 

3-port switch 

Supports two MAC-NETs 

Supports 64-bit Atlantic/FIFO 

ports 

IEEE 1588 support 

Fast cut-through mode 

QoS with eight queues per port 

Port mirroring 

Level 3 IP snooping 

Configuration 

Statistics 

Register Interface 

• Dual unified DMA 

RX Control 

CRC 

Check 

CRC 

Generate 

Pause 

Frame 

Terminate 

TX Control 

Pause 

Frame 

Terminate 

MDIO 

Master 

MII/RMII 

Receive 

Interface 

MII/RMII 

Receive 

Interface 

PHY 

Management 

Interface 

31


32 

On-chip transmit and receive 

FIFOs 

Supports legacy buffer 

descriptor programming models 

and functionality 

Enhanced buffer descriptor 

programming model for new 

Ethernet functionality 


Clocking Options 

The Ethernet subsystem uses the 

following clocks: 

• Dedicated on-chip PLL with fixed 

multiplier to generate 50 MHz RMII 

Ethernet clock. This clock also 

comes as chip output and goes to 

off-chip Ethernet PHY 

• Optional externally-supplied 50 MHz 

RMII clock. This clock is used as 

the timing reference for the RMII 

interface 

• A time-stamping clock for the IEEE 

1588 timers 

IEEE 1588 Timers 

The Ethernet module includes a fourchannel 

timer module for IEEE 1588 

time stamping. The timer supports 

input capture (rising, falling or both 

edges) and output compare (toggle 

or pulse with programmable polarity). 

The counter is able to operate 

asynchronously to the Ethernet bus 

by using one of the clock sources. 

Ethernet Operation in 

Low-Power Modes 

Ethernet-Only Operation 

The Ethernet MAC supports magic 

packet detection that can generate a 

wakeup in low-power mode. During 

low-power operation: 

• The MAC transmit logic is disabled 

Adjustable Timer 

ENETn_ATPER 

Correction 

Counter 

ENETn_ATINC 

ENETn_ATINC 

[INC_COR] 

Counter 

Mod 

• The core FIFO receive/transmit 

functions are disabled 

• The MAC receive logic is kept in 

normal mode but it ignores all traffic 

from the line except magic packets 

Dual Ethernet and L2 Switch 

Operation 

In low-power STOP mode, the 

MAC stops immediately and freezes 

register values, state machines and 

external pins. During this mode, 

the Ethernet subsystem clocks are 

shut down. Coming out of STOP 

mode returns the Ethernet MAC 

to operating from the state prior to 

STOP mode entry. 

External 

Free-Running 

Counter 

ENETn_ATINC 

[INC] 


ENETn_ATCR 

[SLAVE] 

To MAC 

Dual Ethernet and L2 Switch 

Bypassed 

In low-power STOP mode, the MAC 

stops immediately and freezes register 

values, state machines and external 

pins. During this mode, the Ethernet 

subsystem clocks are shut down. 

Coming out of STOP mode returns the 

Ethernet MAC to operating from the 

state prior to STOP mode entry. 

Battery Mode of Operation 

The Ethernet MAC does not support 

any standby mode of operation or a 

capability to operate on battery power 

in case the main supply fails. The 

MAC will be disabled during 

this mode.


USB Subsystem 

Flexible USB connectivity with integrated PHY 

The USB subsystem in Vybrid devices 

is comprised of several blocks 

that together provide flexible USB 

functionality. The USB subsystem 

includes: 

• Dual USB On-The-Go (OTG) 

2.0 compliant controller (specific 

controller depends on the device). 

Options are: High-Speed (HS), Full- 

Speed (FS) and Low-Speed (LS) 

• Dual on-chip HS USB PHY 

• USB regulator 

USB Controller 

The USB controller is a USB 

2.0-compliant serial interface engine 

for implementing a USB interface. The 

USB controller provides USB host 

and device communications along 

with support for OTG operation. The 

controller supports HS, (480 Mbps), 

FS (12 Mbps) and LS (1.5 Mbps) 

data transfer rates. The registers and 

data structures are based on the 

enhanced host controller interface 

specification (EHCI) for USB standard. 

The USB OTG module can act as a 

host or device. The USB controller 

is programmable to support host or 

device operations under firmware 

control. On-chip HS PHY is used 

for the 60 MHz clock source to the 

controller. The USB controller provides 

control and status signals to interface 

with external USB OTG and USB 

host power devices. Customers can 

use these control and status signals 

on the chip interface and the I 2 C bus 

to communicate with external USB 

On-The-Go and USB host power 

devices. USB host modules must 

supply 500 mA with a 5V supply 

on its downstream port (referred to 


USB OTG/HOST PHY Architecture 

BIAS 

PLL 

Common 

Block 

OTG 

as VBUS), however, the USB OTG 

standard provides a minimum 8 mA 

VBUS supply requirement. If the 

connected device attempts to draw 

more than the allocated amount of 

current, the USB host must disable the 

port and remove power. USB VBUS is 

not provided on-chip. The Vybrid SoC 

provides pins for control and status to 

an external IC capable of managing 

the VBUS downstream supply. 


HS/FS/LS 

Receivers 

Squelch/ 

Disconnect 

Clock 

Buffers 

Receiver 

Transmitter 

Local Bias 

D+/D- Pull-up/ 

Pull-down Logic 

HS/FS/LS 

Transmitters 

Single-Ended 

Receivers 

Analog Block 

HS/FS/LS 

Receivers 

Squelch/ 

Disconnect 

Clock 

Buffers 

Receiver 

Transmitter 

Local Bias 

D+/D- Pull-up/ 

Pull-down Logic 

HS/FS/LS 

Transmitters 

Single-Ended 

Receivers 

Analog Block 

Test 

Interface 

HS DLL 

Elasticity 

Buffer 

FS DPLL 

HS 

FS 

Transceiver 

MUX 

Test 

Interface 

HS DLL 

Elasticity 

Buffer 

FS DPLL 

HS 

FS 

Transceiver 

MUX 

SYNC 

Detector 

MUX 

FS/LS 

NRZI 

Decoder 

NRZI 

Encoder 

Bit 

Unstuffer 

Receive 

State 

Machine 

Transmit 

State 

Machine 

Bit 

Stuffer 

USB 1.1 

Transceiver 

FS/LS 

Digital Block 

SYNC 

Detector 

MUX 

FS/LS 

NRZI 

Decoder 

NRZI 

Encoder 

Bit 

Unstuffer 

Receive 

State 

Machine 

Transmit 

State 

Machine 

Bit 

Stuffer 

USB 1.1 

Transceiver 

FS/LS 

Digital Block 

Rx Shift 

and Hold 

Control 

Logic 

Tx Shift 

and Hold 

Rx Shift 

and Hold 

Control 

Logic 

Tx Shift 

and Hold 

For OTG operations, external circuitry 

is required to manage the host 

negotiation protocol (HNP) and session 

request protocol (SRP). External ICs 

that are capable of providing the OTG 

VBUS with support for HNP and SRP, 

as well as support for programmable 

pull-up and pull-down resistors on the 

USB DP and DM lines, are available 

from various manufacturers. 

33


Features 

• Complies with USB specification 

rev 2.0 

• USB host mode 

Supports EHCI 

34 

Supports HS operation using 

internal on-chip HS PHY 

Supported by Linux ® and other 

commercially available operating 

systems 

• USB device mode 

Supports HS operation using 

internal on-chip HS PHY 

Supports FS/LS operation using 

internal HS PHY 

Supports one upstream facing 

port 

Supports six programmable, 

bi-directional USB endpoints, 

including endpoint 0 

• Suspend mode/low-power 

As host, firmware can suspend 

individual devices or the entire 

USB and disable 

Chip clocks for low-power 

operation 

Device supports low-power 

suspend 

Remote wakeup supported for 

host and device 

Integrated with processor doze 

and stop modes for low-power 

operation 

Start of Frame 

USB audio use cases require some 

sort of audio clock recovery capability. 

The Vybrid system USB OTG controller 

supports use of the start of frame 

(SOF) signal, which is generated at 

the start of a microframe in the USB 

2.0 HS protocol. This is a signal with 

a rate of 125 microseconds. When 

operating in full-speed mode, the SOF 

SOF Implementation on the Vybrid Platform 

USB OTG 0 

USB OTG 1 

USB0 SOF 

USB1 SOF 

signal has a rate of 1 ms pulse that 

asserts for 64 system clock cycles 

when the SOF token is detected on 

the USB bus and the USB controller is 

in device mode. 

In order to properly support USB audio 

isochronous asynchronous mode of 

operation, it is necessary to measure 

how many audio sample clock ticks 

occur between two consecutive 

occurrences of the SOF signal. This 

measurement is used to provide 

feedback to the USB audio source in 

order to speed up or slow down the 

audio sample delivery over the USB 

bus. 

This is the method of estimating the 

ratio between the USB host clock 

(SOF occurrences) and the Vybrid 

device local audio clock. 

The figure above shows the USB SOF 

connectivity with FlexTimer to enable 

this scheme. 

FTM0 

FTM1 

FTM2 

FTM3 


64 Cycles 

Pulse 

Stretcher 

64 Cycles 

Pulse 

Stretcher 

1. The two SOF signals (one from each USB port) must be brought to two timer 

channels of one FlexTimer. This flexibility is provided in FTM2 and FTM3 as 

shown in figure. 

2. At least one of the SOF should be connected to one channel of a second 

FlexTimer. This will allow measuring of two sets of audio clock/SOF signals. 

To accommodate this, the USB0 SOF is connected to all FlexTimers. 

USB OTG/HOST PHY 

Architecture 

USB0 SOF_PULSE 

USB1 SOF_PULSE 

Audio Master Clock should also be provided as one of the clock options to FlexTimers. 

The USB OTG HS PHY is a HS/FS/ 

LS USB 2.0 PHY, integrated with the 

controller. 

The USB OTG HS HY comprises two 

USB 2.0 transceiver sub-modules, one 

OTG sub-module and one common 

module shared between USB OTG 

and USB H1 channels. 

USB OTG PHY Features 

• Complete physical interface module 

for USB 2.0 On-the-Go 

• UMTI+ Level 3 specification compliant 

• Supports USB HS (480 Mbps), FS 

(12 Mbps) and LS (1.5 Mbps) 

• Host, slave and OTG dual role device 

operational modes of OTG port 

• Host modes of host port 

• Integrated self-calibrated 

termination resistors for HS mode 

and full set of pull-up/pull-down 

resistors defined by USB 2.0 

electrical requirements


Memory Subsystem 

Flexible memory hierarchy for optimal code footprint, 

security and BOM cost 

Vybrid devices have multiple memory 

interface options. In addition to 

having up to 1.5 MB of on-chip 

SRAM for speedy code execution, 

Vybrid devices can interface to a 

variety of external peripherals and 

memories for system expansion 

and data storage. Dual Quad SPI 

interfaces with Execute-in-Place (XiP) 

support can interface with the latest 

flash memory. A secure digital host 

controller supports SD, SDIO, MMC 

or CE-ATA cards for in-application 

software upgrades as well as media 

files or adding Wi-Fi ® support. NAND 

flash and DRAM controllers with ECC 

support allow connection to a wide 

variety of memory types for critical 

applications. Battery-backed RAM is 

critical for secure systems to store 

authentication keys. Vybrid devices 

provide 16 KB of secure RAM and the 

platform provides 96 KB ROM for high 

assurance boot. 

The “Vybrid Memory Hierarchy” 

diagram illustrates the memory 

hierarchy of Vybrid devices and the 

various memory interfaces. 


Tag 7 

(Optional) 

Vybrid Memory Hierarchy 

Tag 6 

0 

0 

Data 

7 

ARM ® Cortex-A5 Core Complex 

ITM + ETM + ETB + CTI 

FPU + NEON 

Inst 

Alu/ Q 

Mul Ld/Sc Shift 

Data uTLB 

STB 

D-$ 

4 x 8K 

AXI System Bus 

TLB 

AXI-BIU 

PFU & Branch 

Predictor 

Inst uTLB 

L2 Cache Controller 

Vybrid DRAM Controller 

I-$ 

2 x 16K 

NIC-301 

SDIO x2 NAND Flash DDRC Quad SPI x2 OCRAM 

_sys 

Network 

Inter-Connect 

(NIC) 

64-bit AXI 

64-bit AXI 


64 

64 

Multi-Port 

Arbitration 

Arbitration 

Engine 

OCRAM 

_sys 

OCRAM 

_gfx 

TPIU 

DAP 

DRAM Memory Controller 

Command 

Queue 

Ordering 

Engine 

Write 

Queue 

Read 

Queue 

Transaction 

Processing 

Sequence 

Engine 

Performance 

and Power 

Tuning 

Registers 

RAM 

Array, 32k 

Tag/Data 

Arrays, 2x 8k 


Core Complex 

NVIC 

FPU 

CM4 CPU 

FPB 

DWT CTI 

AP Bus Matrix ITM 

System Bus Code Bus 

TCMU 

Sys-$ 

Sys BIU Code BIU 

TCML 

Code-$ 

RAM 

Array, 32k 

Tag/Data 

Arrays, 2x 8k 

64 64 64 

AHB System Bus AHB Code Bus AHB Backdoor Port 

Boot 

ROMx2 

DFI Interface DFI Interface 

FlexBus PBRIDGE 

PHY 

Interface 

DLL 

ECC 

Device 

Interfaces 

DRAM 

DDR3 

LPDDR2 

35


Vybrid DRAM Controller 

The Vybrid DRAM controller offers 

connectivity with application interfaces 

on one side and DRAM memory on 

the other. 

Vybrid DRAM Features 

• Supports 8-bit and 16-bit DRAM 

memories 

• Supports two 64-bit AXI port slave 

interfaces 

• Support for synchronous and 

asynchronous modes 

• Supports components up to 8 GB 

• Supports LPDDR2 (S2 and S4) and 

DDR3 

Supported LPDDR2 grades: 

LPDDR2-800 and under 

Supported DDR3 grades: 

DDR3-800 

• ECC support (only for 8-bit DRAM 

interface) 

• DFI interface to PHY 

Quad SPI 

Vybrid device’s QuadSPI implements a 

Double Data Rate interface, enhanced 

read data buffering schemes, XiP 

and support for dual-die flashes. 

Quad serial flash memories with DDR 

interfaces are available on the market 

with throughput up to 66 Mbps 

peak data rates. With a dual Quad 

SPI architecture this is increased to 

132 Mbps. An enhanced read data 

buffering architecture, minimizes the 

latency impact of cache misses. Only 

the CPU will access the Quad SPI in 

the XiP mode of operation. The 

36 

Vybrid NAND Flash Controller Block Diagram 

boot_after_reset 

lpg_clk 

lps_clk 

reset_b 

IPS BUS CPU Access Bus 

boot_done 

Boot 

Control 

CMD 

Data 

Control 

Register 

Config 

Addr 

Dec. 

DMA 

Control 

boot_fail 

IPM DMA Bus 

boot_mode 

external serial flash can be used at 

runtime for data storage (graphics, 

fonts etc.). It can also contain the 

application code image that will be 

copied to external DRAM at boot. 

Residue 

Generation 

Control 

BCH Encoder 

Seven ECC 

Modes 

ECC Control 

BCH 

Decoder 

Quad SPI Features 

• Double data rate support for 

Spansion (data learning) and 

Macronix (DTR2 mode) serial flash 

• XiP 

• Multi-master buffering support 

• Up to four independent master 

channels 

• Support for dual-die packages with 

two chip selects 

SRAM 

Control 


SRAM 

Buffer 

BUS 

SRAM Buffer 

9 KB 

NAND FLASH CONTROL 

EMB IF 


The NAND flash controller (NFC) 

interfaces standard NAND flash 

devices with Vybrid devices and hides 

the complexities of accessing the 

NAND flash. It provides a seamless 

interface to both 8- and 16-bit NAND 

flash parts with page sizes of 512 

bytes, 2 kilobytes, 4 kilobytes and 

8 kilobytes. 

There are two specific use-cases for 

NAND flash usage with Vybrid devices. 

a) Boot from NFC: This allows systems 

to directly boot from external NAND 

memory. Bootloader may either 

reside in ROM or external NAND 

device while the OS kernel would be 

part of external NAND memory. 

irq 

NFC_IO[15:0] 

NFC_CLE 

NFC_ALE 

NFC_CEn 

NFC_RE 

NFC_WE 

NFC/R/Bn 

REQ 

IDLE 

GRT


Secure Digital Controller 

For the cases where ROM includes 

the bootloader (most likely), the 

system will boot from ROM, jump 

to external NFC and continue 

loading the OS kernel. For the cases 

where a bootloader as well as OS 

kernel resides in the external NAND 

memory, system will switch to 

external NFC after ROM initialization. 

b) NFC for bootloader: After ROM 

initialization, system switches to 

external NAND device to load the 

bootloader. 

Features 

• NAND flash interface: 8-bit/16-bit 

• Supports all NAND flash products 

regardless of density/organization 

(with page sizes of 512+16B/2K+64 

B/4K+128B/4K+218B/8K) 

• Supports flash device commands 

such as page read, page program, 

reset, block erase, read status, read 

ID, copy-back, multi-plane read/ 

program, interleaved read/program, 

random input/output and read in 

EDO mode, but is not limited to 

these commands 


Enhanced Secure Digital Host Controller 

DMA 

Interface 

AHB Bus 

IP Bus 

Transceiver 

IP Gasket 

IP Bus 

• Two configurable DMA channels 

• Bypassable ECC mode, NFC 

supports 4/6/8/12/16/24/32-bit 

error correction 

Secure Digital Controller 

The SD host controller version 

provides an interface between the 

host system and SD, SDIO, MMC or 

CE-ATA cards. The module has a builtin 

transceiver as shown in the figure 

above. The SDHC acts as a bridge, 

passing host bus transactions to SD/ 

SDIO/MMC/CE-ATA cards by sending 

commands and performing data 

accesses to/from the cards. It handles 

SD/SDIO/MMC/CE-ATA protocols at 

the transmission level. 

The SD card is designed to meet the 

security, capacity, performance and 

environmental requirements inherent 

in newly emerging audio and video 

consumer electronic devices. The 

physical form factor, pin assignment 


Card 

and data transfer protocol are forward 

compatible with the multimedia card 

with some additions. 

The Vybrid family has two SDHC 

controllers, supporting up to an 8-bit 

interface for high-speed MMC/SDIO 

cards. 

SDHC Features 

• Conforms to SD Host Controller 

Standard Specification version 2.0 

• Compatible with the MMC System 

Specification version 4.2 

• Compatible with the SD Memory 

Card Specification version 2.0 

• Supports high capacity SD memory 

card 

• Compatible with the SDIO Card 


• Compatible with the CE-ATA Card 


• Supports 1-bit/4-bit SD and SDIO 

modes, 1-bit/4-bit/8-bit MMC 

modes, 4-bit/8-bit CE-ATA devices 

• Up to 200 Mbps data transfer for 

SD/SDIO cards using four parallel 

data lines 

• Up to 416 Mbps data transfer for 

MMC cards using eigiht parallel data 

lines 

37


FlexBus 

The FlexBus interface on the Vybrid 

devices is designed to gluelessly 

connect with up to six external 

devices. Each version has 8-, 16- and 

32-bit port sizes with configuration 

for multiplexed or non-multiplexed 

addresses and data buses. 

Features 

• Byte-, halfword-, word- and 16-byte 

line-sized burst transfers 

• Programmable burst and burst 

inhibited transfers selectable for 

each chip select and transfer 

direction 

• Auto-acknowledge feature 

Primary wait state counter up to 

63 clocks 

Optional secondary wait state 

counter 

Useful for interfacing to burst 

memories that have a long 

access time for the first beat of 

data, but can deliver subsequent 

data faster 

• Programmable address setup time 

with respect to the assertion of chip 

select 

• Programmable address hold time 

with respect to the negation of chip 

select and transfer direction 

Flexbus supports the connection to: 

• Flash 

• Smart LCDs 

• FPGAs 

• SRAM 

• PROM 

• EPROM 

• EEPROM 

38 

FlexBus Modes of Operation of Operation 

Non Muxed Mode 

FlexBus Key Features Customer Benefits 


8-, 16-, 32- and 128-bit line sized transfers Maximize throughput according to the specific 

application 

Programmable burst and burst-inhibited transfers 

selectable for each chip select and transfer 

direction 

Optimized traffic patterns for each client in 

the bus 

Auto-acknowledge feature Increased flexibility and lower BOM costs in 

glueless external device connections 

Programmable address-setup time 

Programmable address-hold time 

Data Data Data Data 

Address Address Address Address 

Data and Address Have Separate Ports 

Muxed Mode 

Address Data Data Address 

Data and Address Are Interleaved on the Same Port 

Smart LCD Mode 

Data Data Data Data 

Data Is Sent Sequentially on One Port


The universal asynchronous receiver/ 

transmitter (UART) module in Vybrid 

devices allows for asynchronous, 

full-duplex serial communication in a 

variety of formats. 

Features of the UART include: 

• Standard mark/space non-return-tozero 

format 

• Supports IrDA 1.4 return-to-zeroinverted 

format 

• Supports ISO 7816 protocol for 

interfacing with SIM cards and 

smartcards (feature supported on 

one UART module only) 

• 13-bit baud rate selection with 

by-32 fractional divide 

• Programmable eight- or nine-bit 

data formats 

• Ability to select MSB or LSB to be 

first on the wire 

• Hardware flow control support for 

request to send and clear to send 

signals 

• Separate transmit and receive 

(feature supported on two UART 

modules only) FIFOs with DMA 

request capability 

ISO 7816 Support 

Two of the UART modules support 

the ISO 7816 standard, allowing 

communication with SIM cards and 

smartcards. This feature has the 

following characteristics: 

• Supports T=0 and T=1 protocols 

• Automatic retransmission 

of NACKed packets with 

programmable retry threshold 

• Supports 11 and 12 ETU transfers 

• Detects initial packet and automated 

transfer parameter programming 


UART Transmit Logic 

UART Transmit Logic 

Module 

Clock 

ISO ISO 7816 7816 Timing Timing Diagrams Diagrams 

ISO 7816 Format without Parity Error (T=0) 

START 

BIT 

BIT 0 

BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 

PARITY 

BIT STOP 

BIT 

STOP 

BIT 

ISO 7816 Format with Parity Error (T=0) 

START 

BIT 

BIT 0 

ISO 7816 Format (T=1) 

START 

BIT 

Baud Rate Generator 

SBR12:0 BRFA4:0 

PE 

PT 

BIT 0 

M10 

M 

TXINV 

MSBF 

Parity 

Generation 


Universal Asynchronous Receiver/ 

Transmitter 

A flexible approach to full-duplex serial communication 

Stop 

IRQ/DMA 

Logic 

Internal Bus 

SCI Data Register (SCID) 

Variable 12-bit Transmit 

Shift Register 

Shift Direction 

7816 Logic 

Infrared Logic 

Start 

Transmitter 

Control 

TXDIR 

SBK 

TE 


PARITY 

BIT 


PARITY 

BIT 

R485 Contol 

Loop Control To Receiver 

NACK 

ERROR 

STOP 

BIT 

TXD Pin Control 

Tx port en 

Tx output buffer en 

Tx input buffer en 

DMA Done 

TxD 

NEXT 

START 

BIT 

TxD 

DMA Requests 

IRQ Requests 

LOOPS 

RSRC 

RTS_B 

CTS_B 

NEXT 

START 

BIT 

STOP 

BIT 

NEXT 

START 

BIT 

39


• Interrupt-driven operation with seven 

ISO-7816 specific interrupts: 

Wait time violated 

40 

Character wait time violated 

Block wait time violated 

Initial character detected 

Transmit error threshold 

exceeded 

Receive error threshold 

exceeded 

Guard time violated 

Variety of Communications 

Formats Available 

The UART offers a number of options 

for data size, format and transmission/ 

reception settings. The variety of 

available options makes the UART 

capable of implementing a wide variety 

of serial communications protocols. 

Features 

• Eight- and nine-bit data formats 

supporting parity over all nine bits 

• MSB or LSB first on wire 

• Programmable transmitter output 

polarity 

• Programmable receiver input polarity 

FIFOs with DMA 

Request Capability 

The UART FIFOs reduce the frequency 

of CPU processing required by the 

UART. 

The DMA can be configured to 

transfer an entire packet of data and 

then interrupt the CPU when all bytes 

are received. This means the CPU can 

process the entire packet all at once 

instead of needing to stop the current 

program flow to move data bytes as 

they are received. 

The size of the FIFOs vary depending 

on the particular device and the 

specific UART. The Vybrid platform 

supports 16-byte FIFO on two UARTS 

(UART0 and UART1) and 8-byte FIFO 

on the other UARTS (UART2, UART3, 

UART4, UART5). 

UART UART Receive Receive Logic Logic 

Module 

Clock 

RxD 

LOOPS 

RSRC 

From 

Transmitter 

RxD 

SBR12:0 BRFA4:0 

RE 

RAF 

Baud Rate 

Generator 

Receive 

Control 

Receiver 

Source 

Control 

Active Edge 

Detect 

UART UART Data Data Formats Formats 

Infrared Logic 

Eight Bits of Data with LSB First 

START 

BIT 

BIT 0 

Internal Bus 

Stop 

Data Buffer 

Variable 12-bit Receive 

Shift Register 

Shift Direction 

PE Parity 

PT 

Logic 


Start 

Wakeup 

Logic 

7816 Logic 

IRQ/DMA 

Logic 

BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 

ADDRESS 

MARK 

BIT 7 STOP 

BIT 

Eight Bits of Data with MSB First 

ADDRESS 

MARK 

START 

BIT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 

M 

M10 

LBKDE 

MSBF 

RXINV 

DMA Requests 

IRQ Requests 

To TxD 

START 

BIT 

Nine Bits of Data with LSB First 

ADDRESS 

MARK 

START 

BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP 

BIT 

Nine Bits of Data with MSB First 

ADDRESS 

MARK 

START 

BIT BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 

STOP 

BIT 

BIT 0 

START 

BIT 

STOP 

BIT 

START 

BIT 

START 

BIT

Software and Development Tools


Freescale Virtual Hardware Platform 

A rapid product development tool designed to 

accelerate software development 

Vybrid families support a wide variety 

of complex I/O controllers, display 

subsystems and communication 

interfaces while supporting a highly 

configurable multicore and multimemory 

programmer’s model. Vybrid 

families are designed to efficiently 

handle numerous applicationlevel 

design challenges as well as 

traditional real-time embedded tasks. 

This is where our virtual hardware 

platform provides an additional 

resource for managing the design and 

debug of your application. 

The virtual hardware platform brings 

many features found in standard 

desktop virtual machine environments 

to embedded customers who need 

a platform to accelerate software 

development. Unlike traditional 

modeling environments, this tool 

leverages a fast instruction set model 

that runs natively with no code 

conversion requirements between x86 

and ARMV7. 

42 

This is combined with broad system 

modeling techniques, resulting in a 

Vybrid device with an example EVB 

hardware environment that can be 

virtually represented on any Windowsenabled 

machine. 

Features 

• Single executable product that loads 

editable data-driven files 

Editable bootimages 

Peripheral parameters 

(e.g., target display screen 

parameters) 

Feature/mux configurations on 

select features (I/Os, UARTs, 

GPIOs) 

EVB memory sizes (editable 

virtual machine configuration 

files to set EVB memory) 

• Fast instruction execution for one or 

both ARM ® cores 

Full support for ARM 

Cortex-A5 and ARM 

Cortex-M4 cores as 

implemented in Vybrid families 

Code execution capable of 

running high-level operating 

systems (Linux ® or others) at 

chip-level performance or faster 

• Bridged peripheral support between 

host platform and embedded virtual 

machine 

File system on host machine can 

be mapped to embedded virtual 

machine file system 

– Allows rapid testing of board 

support/processor support 

packages 

– Allows rapid application 

development (JAVA, 

Android ® , Linux, MQX 

and others)


Diagram of Virtual Hardware Platform 

Embedded VM: Laptop Boundary 

Embedded VM: EVB Boundary 

Embedded VM: eMPU Boundary 

Cache 

VM-Cores 

A5 M4 

System Visiblity 

Trace Data 

IDE Tool 

Plug-ins 

Ethernet nodes on host machine 

can be mapped to Ethernet 

nodes on virtual target (Ethernet 

bridging ability) 

Display controller output to host 

machine display 

– Leverage GUI development 

packages to develop and test 

HMI/UI applications, on virtual 

display controllers. Control 

one or two screens at the 

same time 


SRAM 

Ethernet 

Memory 

Subsystem 

Display 

Control 

Comm 

System 

Serial 

Flash 

NAND 

Flash 

Virtual 

Comm Ports 

(UARTs) 

Serial interface input and capture 

– Configure test files to 

generate/receive serial 

communications for testing 

and validating code 

– Leverage virtualized UARTs in 

Windows to transmit/receive 

live data with model 


DDR 

Ethernet 

VM Bridge 

File 

System/ 

Bridge 

Windows 

Frame 

Buffer 

Frame 

Buffer 

Config 

Laptop 

Ethernet/Wi-Fi ® 

Laptop File System 

Laptop LCD 

Screen 

Internal/External 

Window 

Virtual 

Screen 1 

Window 

Virtual 

Screen 2 

Network 

• Advanced debugging features 

Industry-leading IDE support 

allows real-time debug, trace, 

and visibility to internal debug 

data providing enhanced 

application-level development 

Debug access available through 

Windows DLL extensions 

43


Freescale MQX Software Solutions 

Complimentary full-featured RTOS 

Freescale streamlines 

embedded design with 

a complimentary RTOS 

and software stacks 

The increasing complexity of 

industrial applications and expanding 

functionality of semiconductors 

are driving embedded developers 

toward solutions that combine proven 

hardware and software platforms. To 

help accelerate time to market and 

improve application development 

success, Freescale offers the MQX 

RTOS with TCP/IP and USB software 

stacks and peripheral drivers to 

ColdFire, ColdFire+ and Kinetis MCU 

customers at no additional charge. 

The combination of Freescale MQX 

software solutions and our silicon 

portfolio creates a comprehensive 

source for hardware, software, tools 

and services. 

44 

Freescale Comprehensive Solution Solution 

CodeWarrior 

Development 

Environment 

(MQX OS 

Aware) 

CodeWarrior 

Processor 

Expert 

MQX Design 

and 

Development 

Tools 

Third Party: 

IAR ® 

ARM ® , Keil 

(MQX OS Aware) 

Open Source 

BDM and 

Third Party: 

Emulator/Probe 

PC Hosted 

Freescale MQX Software Solutions 

Reducing Cost, 

Accelerating Success 

Demo Code Applications 

Application Tasks and 

Industry-Specific Libraries 

MQX RTOS 

Optional 

Services 

BDM/JTAG 

By providing complimentary 

Freescale MQX software solutions 

with its silicon products, Freescale 

helps alleviate much of the initial 

software investment hurdle faced by 

embedded developers. Comparable 

full-featured software offerings may 

cost developers as much as $95,000 

(USD) in licensing fees. 

Ethernet 

(RTCS) 

File System 

Core Services MQX RTOS 

BSP/PSP 

On Device 

USB 

CAN 

MCU 

Customized 

Applications 


Discrete 

Driver, 

Third 

Party 

and 

Freescale 

Application 

Enablement 

Layer 

HAL 

Hardware 

According to recent research, 

development teams spend 

approximately 60 percent of their 

resources on software. Embedded 

projects based on 32-bit devices have 

a greater need for software reuse to 

manage development costs.


MQX RTOS: MQX Customizable RTOS: Customizable Component Component Set Set 

The Freescale MQX RTOS and 

software stacks address these 

developer needs by providing a 

scalable, reusable platform that works 

across a wide range of Freescale 

processor architectures, development 

tools and third-party software 

environments. 


Name Services 

Queues Interrupts 

Partitions Utilities 

Messages 

Task 

Management 

Task Errors 

Lightweight 

Initialization 

Core Memory 

Events 

Semaphores 

Services 

CORE 

Watchdogs Mutexes 

Task Queue 

Automatic 

Timers 

Scheduling 

Task Creation 

RR and FIFO 

IPCs 

Formatted I/O 

Scheduling 

Exception 

Handling 

I/O Subsystems Kernel Log 

Logs 

AS-NEEDED 

Freescale MQX is deployed as 

production-ready source code, 

including communications software 

stacks and peripheral drivers, at no 

additional cost. Freescale MQX is 

provided with a commercial-friendly 

software licensing model, enabling 

developers to keep their source 

modifications while being able to 

distribute the required binary code. 


Full Featured, Proven and 

Scalable 

The MQX RTOS has been the 

backbone of embedded products 

based on Freescale silicon for 

more than 15 years. MQX software 

deployment spans a broad range 

of market segments and leading 

manufacturers worldwide. 

The Freescale MQX RTOS offers 

powerful, preemptive real-time 

performance with optimized context 

switch and interrupt time, enabling 

fast, highly predictable response 

times. Its small, configurable size 

conserves memory space for 

embedded applications and it can be 

configured to take as little as 6 KB 

of ROM, including kernel, interrupts, 

semaphores, queues and memory 

manager. 

The Freescale MQX RTOS offers 

a straightforward application 

programming interface with a modular, 

component-based architecture that 

makes it very scalable. Components 

are linked in only if needed, preventing 

unused functions from bloating the 

memory footprint. Plug-ins, such 

as security, industrial protocols and 

graphical interfaces from Freescale’s 

strong network of partners, can also 

be added. 

45


Certifiable to Medical and 

Aerospace Standards 

Even if your application does not 

require formal certification, the 

robustness of MQX provides a 

trusted platform that has been 

proven in thousands of timecritical, 

sophisticated applications. 

For designs that do have a formal 

certification process to follow, 

MQX is an excellent choice. Past 

licensees have certified MQX-based 

applications to medical specifications 

(CFR 820.30 Part 21, IEC 60601- 

1) and the aerospace requirements 

listed under DO-178b. Safetycritical 

applications based on MQX 

include eye surgery equipment, 

drug injection equipment, radiation 

dose monitoring equipment, aircraft 

braking systems and aircraft 

navigation equipment. 

46 

RTCS Tower TCP/IP System StackModules 

RPC 

XDR 

Sockets 

*SSH 

*SSL 

NAT IP 

*XML *SMTP *POP3 HTTP 

RIP 


SNMP 

Telnet FTP TFTP DNS SNTP Web Server 

(v1, v2) 

ICMP 

ARP 

BootP 

IP-E 

DHCP 

TCP UDP 

IPCP 

CIDR 

PPP 

IGMP 

PAP 

CHAP CCP LCP 

Ethernet Serial HDLC 

*SNMP 

(v3) 

*Denotes optional products 

Application Presentation Session Transport Network Data Link Physical


Freescale MQX Add-on Software 

Real-Time TCP/IP Communication Suite 

(RTCS) Optional Components 

Available from 

Embedded Access Inc. 

NanoSSL and NanoSSH Software by 

Mocana Available from freescale.com/ 

nanossl, freescale.com/nanossh 

PEG + Graphics Library 


freescale.com/peg 

SEGGER emWin 

Graphics Library/GUI 

Available from SEGGER Microcontroller 

CANOpen Master/Slave for Embedded 

Devices 

Available from IXXAT, Inc. 

Industrial Network 

and Field Bus Protocols 

Available from IXXAT, Inc. 

SFFS Flash File System 

Available from Embedded Access Inc. 

Freescale eGUI: Graphical LCD Driver 


freescale.com/egui 

MicroBrowsers 

Available from Motomic Software, Inc. 

OS Changer—Reuse Application on MQX 

Available from MapuSoft Technologies 



• Network management: Support for SNMP version 1 and 2 is built into RTCS. EAI offers MQX 

SNMPv3 

• XML parsing and framing: The MQX XML component enables your device to accept data in XML, 

as well as send data packaged in XML 

• Email communication: The MQX SMTP module provides your device with outbound email 

communication and MQX POP3 provides the capability to accept incoming email communication 

• NanoSSH: Provides privacy, authentication and ensures data integrity between a secure server 

and its clients 

• NanoSSL: Cyptographic protocols that provide security for communications over networks such 

as the Internet 

• Portable embedded GUI library designed to provide a professional-quality GUI for embedded 

systems applications 

• Small, fast and easily ported to virtually any hardware configuration capable of supporting 

graphical output 

• emWin is designed to provide an efficient, LCD controller-independent GUI for any application that 

operates with a graphical LCD 

• CANopen is a CAN-based higher layer protocol 

• Developed as a standardized embedded network with highly flexible configuration capabilities 

• Unburdens the developer from dealing with CAN-specific details such as bit-timing and 

implementation-specific functions 

• Profinet RT for I/O device 

• EtherNet/IP for adapter and scanner 

• Ethernet powerlink for managing and controlled nodes 

• EtherCAT for slave nodes 

• SERCOS III for slave devices 

• Precision time protocol IEEE ® 1588-2008 (v2) 

• SFFS is a safe flash file system that can support almost any NOR or NAND flash device 

• Provides a high degree of reliability and complete protection against unexpected power failure or 

reset events 

• Provides wear leveling, bad block handling and ECC K30C algorithms to ensure you get optimal 

use out of a flash device 

• Pre-integrated with the MQX RTOS: allows you to create a robust file system quickly for an embedded 

device using on-chip or on-board flash devices 

The complimentary Freescale embedded graphical user interface (eGUI) allows single-chip MCU 

systems to implement a graphical user interface and drive the latest generation of color graphics 

LCD panels with integrated display RAM and simple serial peripheral interface (SPI) or parallel bus 

interface. 

The uButterfly Browser runs on MQX and browses, parses and renders HTML/CSS content. 

• Browse HTML 4/CSS 2.1 Web pages 

• Enable dynamic HTML, active graphics and media 

• An optional SDK allows browsing embedded/instanced within C, C++ or Qt apps (available as a 

separate product) 

OS Changer is a C/C++ source-level virtualization technology that allows you to easily re-use your 

software developed for one OS on MQX, while providing real-time performance. 

Available OS Changer Porting Kits: 

• VxWorks Porting Kit 

• pSOS Porting Kit 

• Linux/POSIX Porting Kit 

• Windows Porting Kit 

• Nucleus Porting Kit 

• micro-ITRON Porting Kit 

47


Freescale Tower System 

A modular development platform 

Overview 

The Freescale Tower System is a 

modular development platform for 

8-, 16- and 32-bit MCUs and MPUs 

that enables advanced development 

through rapid prototyping. Featuring 

multiple development boards or 

modules, the Tower System provides 

designers with building blocks for entrylevel 

to advanced MCU development. 

Modular and Expandable 

• Controller modules provide easyto-use, 

reconfigurable hardware 

• Interchangeable peripheral modules 

(including communications, 

memory and graphical LCD) make 

customization easy 

• Open-source hardware and 

standardized specifications 

promote the development of 

additional modules for added 

functionality and customization 

Speeds Development Time 

• Open source hardware 

and software allows quick 

development with proven designs 

• Integrated debugging interface 

allows for easy programming and 

run control via standard USB cable 

48 

The Freescale Tower System 

Controller/Processor 

Module (MCU/MPU) 

• Tower MCU/MPU 

board 

• Works stand- 

alone or in 

Tower System 

• Features 

integrated 

debugging 

interface for easy 

programming 

and run control 

via standard 

USB cable 

Secondary 

Elevator 

• Additional and 

secondary serial 

and expansion 

bus signals 

• Standardized signal 

assignments 

• Mounting holes 

and expansion 

connectors for sidemounting 

peripheral 

Peripheral Module 

• Adds features and functionality 

to your designs 

• Interchangeable with other peripheral 

modules and compatible with all 

controller/processor modules 

• Examples include serial interface, 

memory, Wi-Fi ® , graphical LCD, motor 

control, audio, Xtrinsic sensing and high 

precision analog modules 


Primary Elevator 

• Common serial 

and expansion bus 

signals 

• Two 2x80 

connectors on 

back side for easy 

signal access and 

side-mounting 

board (LCD 

module) 

• Power regulation 

circuitry 

• Standardized signal 

assignments 

• Mounting holes 

Size 

• Fully assembled 

Tower System is 

approx. 

3.5” H x 3.5” W x 

3.5” D 

Board Connectors 

• Four card-edge 

connectors 

• Uses PCI Express ® 

connectors 

(x16, 90 mm/ 

3.5” long, 164 pins) 

Tower Plug-In (TWRPI) 

• Designed to attach to modules 

that have a TWRPI socket(s) 

• Adds features and functionality 

• Swappable with other TWRPIs 

• Examples include accelerometers, 

key pads, touch pads, sliders and 

rotary touch pads


Tower System Modules 

Controller/Processor Modules (8-, 16-, 32-bit) freescale.com/TowerController 

Works stand alone or as part of Tower 

System 

Cost Effective 

• Interchangeable peripheral 

modules can be re-used with all 

Tower System controller modules, 

eliminating the need to purchase 

redundant hardware for future 

designs 

• Enabling technologies like LCD, 

Wi-Fi ® , motor control, serial and 

memory interfacing are offered offthe-shelf 

at a low cost to provide a 

customized enablement solution 

Take Your Design 

to the Next Level 

For a complete list of development 

kits and modules offered as part of the 

Freescale Tower System, please visit 

freescale.com/Tower. 


Allows rapid prototyping 

Features open source debugging interface Provides easy programming and run control 

via standard USB cable 

Peripheral Modules freescale.com/TowerPeripheral 

Can be re-used with all Tower System 

controller modules 

Interchangeable peripheral modules: Serial, 

memory, graphical LCD, prototyping, sensor 

Tower Plug-Ins freescale.com/TWRPI 

Designed to attach to any Tower System 

module with a TWRPI socket(s) 

Eliminates the need to buy/develop redundant 

hardware 

Enables advanced development and broad 

functionality 

Adds features and functionality with little 

investment 

Swappable components Allows for design flexibility 

Elevator Modules freescale.com/TowerELEV 

Two 2x80 connectors Provides easy signal access and sidemounting 

board (i.e. LCD module) 

Power regulation circuitry Provides power to all boards 

Standardized signal assignments Allows for customized peripheral module 

development 

Four card-edge connectors available Allows easy expansion using PCI Express ® 

connectors (x16, 90 mm/3.5” long, 164 pins) 

Partner Modules 

Tap into a powerful ecosystem of 

Freescale technology alliances for 

building smarter, better connected 

solutions. Designed to help you 

shorten your design cycle and get 

your products to market faster, these 

technology alliances provide you with 

access to rich design tools, peripherals 

and world-class support and training. 

A number of partners have developed 

modules for the Tower System. Some 

examples include the i.MX515 ARM ® 

Cortex-A8 Tower Computer Module 

and StackableUSB I/O Device Carrier 

module from Micro/sys, as well as 

the rapid prototyping system (RPS) 

AM1 and FM1 modules from iMN 

MicroControl. 


Tower Geeks Online Community 

TowerGeeks.org is an online design 

engineer community that allows 

members to interact, develop designs 

and share ideas. Offering a direct 

path to explore and interact with other 

engineers designing with the Tower 

System, TowerGeeks.org is a great way 

to discuss your projects, post videos of 

your progress, ask questions through 

the forum and upload software. With 

updates through Twitter and Facebook, 

it’s easy to get involved. 

Follow Tower Geeks on Twitter 

twitter.com/towergeeks 

Visit Freescale on Facebook 

facebook.com/freescale 

49


Swell PEG Product Line 

Any LCD. Anywhere. PEG Software. 

Swell Software provides graphical 

user interface solutions for embedded 

devices. Swell’s PEG Pro, PEG+ and 

C/PEG product offering includes a GUI 

library for embedded development that 

works tightly with real-time operating 

systems. These development tools 

allow developers to lay out user 

interface screens and controls using 

the PEG library and external resources 

to generate C or C++ code. 

PEG software accelerates GUI design 

for embedded devices by allowing 

developers to create prototypes on 

a Windows ® or Linux ® based PC. It 

provides a complete visual layout and 

design tool to enable GUI design to 

take place in parallel to the embedded 

software/hardware development. 

The PEG WindowBuilder automatically 

generates C or C++ source code that 

is ready to be compiled and linked 

into any application, accelerating the 

deployment of the final product. 

Swell’s GUI software products work 

hand in hand with Freescale customers’ 

real-time operating systems to 

incorporate LCD screens, display and 

input interfaces into future products. 

GUI Interface Technology 

PEG’s modular form enables a 

rapid development process. The 

core library interfaces to different 

50 

GUI Interface Technology 

RTOS 

Application Layer 

RTOS 

Driver 

PEG Library 

LCD Driver 

LCD Driver 

Input 

Driver 

Window Builder Technology 

PEG Pro PEG+ C/PEG 

• Screen transitions 

• Multiple alpha-blended 

windows 

• True anti-aliasing 

• Gradient manager 

• Open GL support 

• Written in C++ 

real-time operating systems, input 

devices and LCD controllers by 

replacing the underlining driver. 

PEG WindowBuilder for 

Rapid Development 

WindowBuilder allows a designer to lay 

out each of the screens for a project 

through a simple-to-use interface. 

• Full WYSIWYG development 

• Runs on PC/Linux/X11 to allow 

proof of concept development 

• Multiple window updates 

• Alpha-blended images 

• Run-time image decoders 

and language resources 

• Custom widget integration 

• Dynamic themes 

• Written in C++ 


• Designed for small LCDs 

(QVGA) 

• Low color-depth 

• Very small footprint 

• Single window update 

• Multi-language capable 

• Written in ANSI C 

One of the smallest footprints and most efficient code bases available. 

Starting 225 KB 

Typical 225–250 KB 

Starting at 160 KB 


Starting at 90 KB 


• Enables hardware/software 

development to happen in parallel 

• Made available for free evaluation 

For more information visit 

freescale.com/peg.


Timesys LinuxLink 

Embedded Linux ® product development made easy 

Timesys helps to eliminate the 

learning time, complexity and risk in 

building and maintaining embedded 

Linux ® devices. As a leader among 

embedded Linux solution providers, 

Timesys offerings are available for 

many Freescale processor families 

including ColdFire, Kinetis, i.MX, 

Vybrid and Power Architecture ® based 

products. 

Timesys offers the award-winning 

LinuxLink embedded development 

system, expert Linux support and 

experienced professional services to 

help development teams bring open 

source Linux-based products to 

market faster and cheaper. 

With a LinuxLink subscription for your 

Freescale processor, you can: 

• Quickly assemble and boot an initial 

embedded Linux image on your 

Freescale development kit. 

• Patch/configure/rebuild/update 

your custom Linux platform on your 

desktop with a properly installed 

and configured development 

environment. 

• Debug/tune the platform with 

common open source development 

tools and development libraries/ 

utilities. 

• Obtain help with common 

development tasks via technical 

assistance and a rich library of 

Timesys-authored “How To” 

documentation. 

Key LinuxLink Components: 

Linux Kernel, Toolchain, Software 

Packages, Bootloader 

All Timesys Linux platforms are built 

and tested for compatibility with our 


Timesys LinuxLink 

Linux Kernel and Drivers 

• Latest open-source kernels 

• ARM ® and other architectures 

• Extensive SoC/device support 

Development Tools/Libraries 

• Latest version of gcc, glibc, uClibc 

• Tested on all supported SoCs 

• Eclipse-based environment 

OS Apps and Middleware 

• Rich selection of packages 

• Networking, industrial, consumer 

• Pre-built, tested, supported 

Boot Loader 

• For supported reference platforms 

• Industry-standard U-Boot 

• Latest open-source code base 

LinuxLink Software Development Framework 

semiconductor partners’ suggested 

bootloader, saving time with initial 

board bring up. 

Factory Distribution Builder 

Timesys’s Factory Distribution Builder 

enables complete customization of 

your Linux platform and integration of 

third-party and proprietary software. 

Also includes innovative “advice” 

and “recommendation” engines to 

minimize mistakes. 

TimeStorm IDE 

TimeStorm’s powerful suite of 

application development tools expertly 

handles embedded chores like crosscompiling 

and remote debugging 

while including support for advanced 

features like profiling, testing and leak 

detection. And TimeStorm is built on 

the Eclipse IDE foundation, a platform 

already familiar to developers. 

Update Notifications 

As a LinuxLink user, you’ll only receive 

automatic notifications of updates 


CHOOSE BUILD DEPLOY 

TimeStorm IDE (Eclipse) 

• Application development and debug 

• Fully integrated with Factory tools 

• Compatible with Eclipse ecosystem 

Factory Distribution Builder 

• Interactive UI with intelligent advice 

• Guides your selection of packages 

• Web (hosted) and desktop versions 

Work Orders 

Updates 

• Automatic kernel updates 

• Automatic middleware updates 

• Web-based and desktop notifications 

Support 

• Web-based 

• In-person 

• Extensive documentation 

Your Custom Tools (SDK) 

• gcc/C library/gdb 

• Relevant application libraries 

Your Custom Image (BSP) 

• Kernel/drivers 

• Root file system 

Ready to run on 

your hardware 

relevant to the Linux components used 

in your software. 

Unmetered Expert Linux Help 

As a LinuxLink subscriber, you’ll have 

access to responsive technical support 

from our expert engineers. Intuitive online 

support enables detailed information 

exchanges and allows you to submit, 

view and update requests, and access 

or reopen resolved requests. 

Get Your Free LinuxLink— 

Build Your Custom BSP/SDK 

in Minutes 

Register for a Free LinuxLink account, 

and assemble a Linux image that you 

can download and run on your board. 

Register at timesys.com/register. 

For more information about Timesys’s 

LinuxLink embedded Linux build 

system, visit timesys.com/linuxlink. 

51


CodeWarrior Development Studio 

Based on the Eclipse open development platform 

The CodeWarrior Development 

Studio for Microcontrollers V10.x 

integrates the development tools for 

the RS08, S08, ColdFire, ColdFire+, 

DSC, Kinetis, Qorivva, PX and 

Vybrid architectures into a single 

product based on the Eclipse open 

development platform. Eclipse offers 

an excellent framework for building 

software development environments 

and is becoming a standard 

framework used by many embedded 

software vendors. 

• Eclipse IDE 3.6 

• Build system with optimizing C/C++ 

compilers for RS08, S08, ColdFire, 

ColdFire+, DSC, Kinetis, Qorivva 

and PX series Power Architecture ® 

cores and Vybrid devices 

• Extensions to Eclipse C/C++ 

development tools (CDT) to 

provide sophisticated features to 

troubleshoot and repair embedded 

applications 

Device/Connection 

Change Wizard 

The Device/Connection Change 

Wizard allows a project to be 

re-targeted to a new processor in 

as few as six mouse clicks. Simply 

select a new device (from the same 

or a different architecture—RS08, 

S08, ColdFire, ColdFire+, DSC, 

Kinetis, Vybrid, Qorivva and PX series 

Power Architecture cores or Vybrid 

devices), select the default connection 

and the CodeWarrior tool suite will 

automatically reconfigure the project 

for the new device with the correct 

build tools and support files. 

52 

C/C++ Perspective 

Device/Connection Change Wizard 

Code Warrior Key Features Key Benefits 


Device Connection Change Wizard Easily retarget project to a new processor 

Trace and profile support for on-chip trace 

buffers 

Sophisticated emulator-like debug capability 

without additional hardware 

LiveView Monitor registers, memory and global 

variables without stopping the processor 

Freescale Processor Expert Problems in hardware layer can be resolved 

during initial design phase


Debug Perspective 

Processor Expert 

Processor Expert Key Features Key Benefits 

Graphical user interface Allows an application to be specified by the 

functionality needed 

Automatic code generator Creates tested, optimized C code tuned to 

application needs and the selected Freescale 

device 

Built-in knowledge base Immediately flags resource conflicts and 

incorrect settings so errors are caught early 

in the design cycle 

Component wizard Allows the creation of user-specific hardwareindependent 

embedded components 



• Compiler 

• Assembler 

• Linker 

• Header files 

• Vector tables 

• Libraries 

• Linker configuration files 

Profiling and Analysis 

The CodeWarrior profiling and 

analysis tools provide visibility into an 

application as it runs on the processor 

to identify operational problems. 

• Supports architectures with 

on-chip trace buffers (RS08, V1 

ColdFire, ColdFire+, Kinetis and 

Vybrid) 

• Allows tracepoints to be set to 

enable and disable trace output 

• Able to step through trace data 

and the corresponding source 

code simultaneously 

• Allows trace data to be exported 

into a Microsoft ® Excel ® file 

Processor Expert 

Freescale’s Processor Expert is a rapid 

application design tool that combines 

easy-to-use component-based 

application creation with an expert 

knowledge system. 

• CPU, on-chip peripherals, 

external peripherals and software 

functionality are encapsulated into 

embedded components 

• Each component’s functionality 

can be tailored to fit application 

requirements by modifying the 

component’s properties, methods 

and events 

• When the project is built, 

Processor Expert automatically 

generates highly optimized 

embedded C-code and places the 

source files into the project 

For more information, visit 

freescale.com/CWMCU10. 

53


ARM ® 

Overview 

The ARM ® Development Studio 

5 (DS-5) is a complete suite 

of software development tools 

for ARM processor-based ASICs 

and standard devices, including 

Freescale’s Vybrid family. DS-5 

accelerates software development 

by providing an easy-to-use, 

integrated and validated toolchain. 

Key Features and Benefits 

• Support for all ARM processors 

• Integration with the industrystandard 

Eclipse IDE, which 

provides a large ecosystem of thirdparty 

plug-ins 

• Flexible C/C++ editor and project 

manager 

• Powerful C/C++ compilation tools 

• Debugger supports all phases of 

development from bootloader to 

kernel, and user space 

• Streamline Performance Analyzer 

provides system-wide profiling 

based on performance counters 

• Instant correlation of performance 

bottlenecks (cache misses, 

interrupts) and software execution 

• Fast simulator for ARM software 

development on the host computer 

with typical speeds above 250 MHz 

• Support and maintenance contract 

for one year 

54 

Development Studio 5 (DS-5) 

The reference software development tool suite for 

ARM ® 

powered platforms 

DS-5 Debugger and DSTREAM 

DS-5 Debugger 

The DS-5 Debugger brings together 

the convenience and productivity of 

integrated embedded development 

tools with the power and flexibility 

of open source tools for Linux ® and 

Android ® . 

The DS-5 debugger provides: 

• Debug of code generated by ARM 

and GNU Compile. 

• Advanced Session Control and 

System Views control multiple 

simultaneous debug sessions, 

to one or more targets, from one 

debugger perspective 

• Run and stop mode debugging of 

single-core and multicore devices 


• Linux kernel and user space debug, 

including context awareness, 

process, and threads 

• Non-intrusive instruction trace 

including summarized profile 

• Conditional and scripted 

breakpoints 

For expert Linux users, DS-5 includes 

the traditional GDB command line 

interface for detailed control of 

target interactions and flexibility 

with scripting advanced debugger 

functions.


Streamline: Timeline and Call Paths 

Call paths view shows the processor time 

spent on each call tree. A flat profiling report is 

generated for the selected call path, which enables 

you to focus the analysis on a process or thread. 

DSTREAM 

The ARM DSTREAM high 

performance debug and trace unit 

enables powerful software debug and 

optimization on any ARM processorbased 

hardware target. 

DSTREAM enables the connection of 

DS-5 Debugger to ARM processorbased 

devices via JTAG or serial-wire 

debug. It uses FPGA acceleration to 

deliver high download speeds and 

fast stepping through code on single 

and multi-processor devices and 

enables: 

• Run control debug and trace unit 

supporting all ARM processors 

• USB 2.0 and Ethernet interface 

allows direct and remote 

connections from the host PC 

• Code downloads at speeds of 

up to 2500 Kbps 

• JTAG clocks of up to 60 MHz 

provide fast software upload over 

the existing debug port 

• 16-bit wide trace capture at 300 

MHz DDR (600 Mbit/s per pin) 


Timeline view shows process and thread 

information over time, matched to SoC 

performance counters. This enables you to 

spot thread deadlocks and inefficiencies, 

as well as hot spots in time. 

• Flexible trace clock positioning 

(relative to trace data) 

• Large 4 GB trace buffer enables 

long-term trace of fast targets 

Streamline 

Streamline is the Linux and Android 

performance analysis tool in DS-5. 

Through a small driver running on the 

target, Streamline captures the target’s 

performance information and displays 

it in an easy to understand graphical 

interface. Streamline includes: 

• Intuitive display of information 

ranging from system-wide 

performance counters to hot 

spots in the source code, making 

it easy for developers to identify 

performance bottlenecks, multithreading 

issues and general 

inefficient resource usage 

• Visualization tools to analyze percore 

performance metrics with 

threads and processes for optimal 

synchronization and concurrency of 

target’s resources 


• Filtering capabilities to restrict the 

data set used by statistical reports 

over time and per-process, thread 

or call path 

• Call paths view shows the processor 

time spent on each call tree. A flat 

report is generated for the selected 

call path, which enables you to 

focus the analysis of a process or 

thread 

• Code View highlights the hot spots 

within a function by displaying the 

processor time spent on each 

line of source code and on each 

disassembly instruction 

• Streamline Capture Options dialogue 

enables you to select the right 

balance between granularity and 

information detail, and intrusiveness 

ARM C/C++ Compiler 

The ARM Compiler in DS-5 

Professional Edition is the only 

commercial compiler co-developed 

with the ARM processors and 

specifically designed to optimally 

support the ARM architecture. It is 

the industry standard C and C++ 

compiler for building applications 

targeting the ARM, Thumb ® , Thumb- 

2, VFP, and NEON instruction 

sets found in the newer Cortex 

processor-based devices. 

ARM processors are designed to best 

execute code generated by the ARM 

Compiler. The ARM Compiler enables 

the new features in all the ARM 

processors. It supports building of 

Symbian OS, ARM Linux, and Android 

native applications and libraries, as 

well as bare-metal applications and all 

major RTOSs. 

Learn more at arm.com/ds5. 

55



Powerful, reliable development tools 

Continuing a long-standing 

relationship with Freescale 

Semiconductor, IAR Systems ® has 

announced that their flagship IAR 

Embedded Workbench ® for ARM ® 

product supports Freescale’s new 

Vybrid devices based on the ARM 

Cortex-A5 and ARM Cortex-M4 

cores. IAR Systems supports nearly 

the entire lineup of Freescale MCUs, 

including the S08, HCS12, ColdFire 

(and all its variants), the Kinetis MCUs 

based on an ARM Cortex-M4 core 

and now Vybrid devices. IAR Systems 

is proud to be allied with Freescale 

in bringing cutting-edge devices and 

tools to our mutual customers. 

IAR Embedded Workbench for 

ARM is a highly efficient and 

independent toolchain that supports 

ARM architectures, including Vybrid 

devices. The Embedded Workbench 

for ARM includes IAR’s IDE, C/C++ 

Compiler, Assembler and Linker to 

give you unparalleled performance. 

56 


Back to Table of Contents


• Ease of use. IAR Embedded 

Workbench for ARM has over 

2,500 example projects to help 

you get your project off the ground 

quickly. These examples are part 

of the installation and are provided 

free of charge. 

• Support for all ARM hardware. 

IAR Embedded Workbench for 

ARM includes support for the 

floating point DSP unit that is 

available in many ARM Cortex-M4 

cores. It also supports the ARM 

Cortex-A5 core and the NEON 

instruction set that is the heart of 

the Vybrid architecture. 

• Tight code generation. The code 

generated is highly optimized 

and IAR Systems encourages 

developers to try out one of the free 

versions (32 kB-limited KickStart 

version or the 30-day evaluation 

version) at iar.com/ewarm to 

compare it to other compilers. 

Prototype your code and see how 

much more efficient IAR is in your 

design. 

• An embedded compiler brings 

you full C++. IAR Embedded 

Workbench for ARM brings 

you full desktop C++ (including 

exception handling, multiple/virtual 

inheritance, etc.) to help you crosscompile 

code and use the bevy 

of test suites available for the PC 

to validate and verify your design 

before it goes into the board. 


Developing your Vybrid device 

application is never easier than 

when you use IAR. 

• Integration to popular sourcecode 

control systems. If you are 

using Subversion or a Microsoft 

Visual Source Safe-compliant 

control system, you can use the 

Embedded Workbench for ARM 

to check code in and out of the 

system to speed your development 

process. 

• Kernel-aware debugging for most 

RTOSs. The C-SPY ® debugger is 

able to do task-aware debugging 

for many popular RTOSs including 

MQX, Micrium uC/OS-II and –III, 

SMX, CMX, Quadros, Sciopta, 

embOS, Express Logic’s ThreadX, 

Free/Safe RTOS and others. This 

awareness allows you to see what 

is happening in your RTOS at a 

glance. 

• Power debugging. IAR Systems 

has a unique power debugging 

feature that allows you to see the 

power being consumed by your 

board when the board is powered 

by a J-Link Ultra. Making your 

design power-efficient used to 

be the domain of only hardware 

engineers, but IAR gives the ability 

to software engineers as well. 


• Local support with global 

reach. IAR Systems has 10 

offices worldwide (including three 

in the United States) and each 

one is staffed with capable and 

experienced engineers who are 

ready to help you with any issues 

that arise. No other compiler 

vendor can claim to have nearly as 

much assistance readily available. 

When considering which toolchain to 

use in your Vybrid design, consider 

the one that was first to support 

Kinetis MCUs, first to support Vybrid 

devices, first in service and first in 

performance: choose IAR Embedded 

Workbench for ARM. 

For more information, please 

email info.us@iar.com. 

57


Atollic tools provide you with powerful 

features that reduce your development 

time and enable you to release a 

software product with higher quality 

with less effort. 

Atollic aims to provide an embedded 

systems toolset that covers all worktasks 

that embedded developers 

are doing on a day-to-day basis. 

The Atollic product portfolio not only 

covers great tools for editing, building 

and debugging but offers powerful 

solutions for team collaboration, 

system and code analysis as well as 

test automation. 

TrueSTUDIO ® : The Embedded 

Systems Development Tool for 

the Next Decade 

Atollic TrueSTUDIO is the premier 

C/C++ development tool for 

embedded systems development, 

with its unrivalled feature-set and 

unprecedented integration. In addition 

to the state-of-the-art editor, the 

optimizing C/C++ compiler and 

multiprocessor-aware debugger with 

tracing support, Atollic TrueSTUDIO 

also includes features for team 

collaboration, graphical modeling 

and design, code review and review 

meetings. 

TrueINSPECTOR ® : Improve 

Software Quality with Static 

Source Code Analysis 

Atollic TrueINSPECTOR is a tool 

for professional code analysis. The 

product performs static source code 

inspection and generates software 

metrics including code complexity 

measurements. The source code is 

validated against a database of 

58 

formal coding standards, and coding 

constructs that are known to be errorprone 

are detected automatically. 

Atollic TrueINSPECTOR supports the 

MISRA ® -C:2004 rule standard. 

TrueVERIFIER: Get Superior 

Software Quality with Embedded 

Test Automation 

Atollic TrueVERIFIER is a tool for 

advanced test automation. The 

product performs source code 

analysis and auto-generate unit-test 

suites that exercise an extensive 

set of different execution paths. The 

tool downloads the test cases and 

runs them in a target board with 

code coverage monitoring. Finally, 

Atollic TrueVERIFIER visualizes the 

test results and the achieved code 

coverage (MC/DC-level). 


Atollic 

World-class tools for embedded systems development 

True Studio 

TrueANALYZER ® : Measure Test 

Quality with Dynamic Execution 

Flow Analysis 

Atollic TrueANALYZER is a tool for 

in-target measurement of test quality. 

The product performs system-level 

dynamic execution flow analysis and 

provides rigorous code coverage 

measurements. Atollic TrueANALYZER 

supports many types of code 

coverage analysis up to the level of 

modified condition/decision coverage 

(MC/DC-level), which is required by 

RTCA DO-178B (Level A) for flightcontrol-system 

software. 

For more information on Atollic tools, 

visit atollic.com.


Multilink and Cyclone 

Debug interfaces and production programming 

P&E’s line of Multilinks and Cyclones 

are powerful solutions that cover the 

complete product cycle. 

USB Multilink Debug 

Interfaces 

P&E’s USB Multilinks are affordable, 

development-oriented interfaces that 

allow access to the debug interface on 

a target MCU from the user’s PC. The 

new Multilink Universal and Multilink 

Universal FX represent the next step 

forward for this very successful line 

of hardware interfaces. They each 

combine support, in a single interface, 

for many Freescale architectures, 

including: Vybrid, Kinetis, HCS08, 

RS08, HC(S)12, ColdFire+/V1, ColdFire 

V2-V4, Qorivva MPC55xx/56xx and 

DSC. The FX version also provides 

much higher communications speeds 

for some architectures (up to a 10x 

speed improvement), and can be used 

to power the target device. These 

“universal” Multilinks include ribbon 

cables to allow connections to all of 

the supported architectures. The user 

can simply flip open the hinged section 

on the Multilink case and install the 

appropriate ribbon cable. 

Multilink and Cyclone 


Multilink Universal and Multilink 

Universal FX Features 

• Draws power from USB interface— 

no separate power supply required 

• Target voltage: 1.6–5.25V 

• Includes a ribbon cable for each 

supported architecture 

• High-speed download (FX version) 

• Can provide target power (FX version) 

Supported Architectures 

• Vybrid 

• Kinetis 

• ColdFire+, ColdFire V1–V4 

• HCS08, RS08, HC(S)12 

• DSC 

Software Support 

• CodeWarrior IDE 

• P&E software (including 

programmers and debuggers) 

• Software tools from IAR, Keil, 

Mentor Graphics, Cosmic, 

and others. Support varies by 

architecture. Contact vendor to 

determine compatibility. 

Cyclone Production 

Programmers 

P&E’s Cyclone products are geared 

towards in-circuit production 

programming, including both 

low-volume, operator-controlled 

programming and high-volume 

automated programming. The Cyclone 

can be used to program both internal 

memory on a Freescale processor/ 

MCU as well as external memory 

connected to the processor’s address/ 

data bus. The processor can be 

mounted on the final printed circuit 

board before programming and does 

not need to be pre-programmed. 


When connected to a PC, the Cyclone 

can communicate via USB, Ethernet, 

or serial port, and its operations can 

be completely automated. In standalone 

mode, programming images are 

first loaded into on-board memory. 

An LCD screen and buttons allow 

one-touch programming operation 

as well as configuration. P&E offers 

automation software packages 

allowing many Cyclone units to be 

“ganged” together. 

The Cyclone may also be used as a 

hardware interface with many popular 

debuggers, similar to the way a USB 

Multilink is used, but also including 

support for Ethernet and serial 

connections. 

Cyclone Features 

• Stores multiple images for 

programming 

• Can be fully automated and 

controlled from a PC 

• Can be controlled via buttons/ 

display without a PC 

• Display for image selection, status, 

and settings 

• Can provide/switch power to target 

• High-speed programming 

• Multiple units may be “ganged” for 

parallel programming 

• Support for dynamic data, including 

serialization 

• May be used as a debug interface 

with many debuggers 

For more information, visit 

pemicro.com. 

59


Designed using SEGGER’s industryleading 

embedded software, J-Link 

debug probes offer a wide array of 

advanced features and boast support 

for a broad spectrum of MCUs and 

MPUs, including Freescale’s complete 

i.MX, Kinetis and ColdFire V2–V4 

lines. Many popular IDEs such as 

CodeWarrior, IAR, Keil, Code Sourcery 

V2–V4 and more have built-in support 

for the J-Link. 

The J-Link debug line offers a high 

download speed into RAM* and flash 

memory. Each JTAG debugger hardware 

model has its own unique attributes and 

offers a number of available software 

add-on modules to enhance the J-Link’s 

functionality. For more details, visit 

segger.com/jlink.html. 

J-Flash is a comprehensive user 

interface for flash programming. The 

flash breakpoint add-on allows for 

an unlimited number of breakpoints 

while debugging in flash memory. The 

J-Link SDK is a standard Windows 

DLL typically used from C. It makes 

the entire functionality of the J-Link 

available through the exported 

functions and allows you to write your 

own program using J-Link. 

Hardware Models 

J-Link Pro for Connectivity 

J-Link Pro is an enhanced version of 

the J-Link. It incorporates an on-board 

Ethernet interface in addition to the 

USB, as well as two LED hardware 

status indicators. It comes with licenses 

for all J-Link related SEGGER software 

products, including flash breakpoints, 

60 

RDI, J-Flash and GDB Server, providing 

the optimum debugging solution for the 

professional developer. 

J-Link ULTRA for High Performance 

J-Link ULTRA is based on the highly 

optimized and proven J-Link. It offers 

even higher speed as well as target 

power measurement capabilities due to 

the faster CPU, built-in FPGA and High- 

Speed USB interface. This permits you 

to take full advantage of the low power 

features offered by today’s modern 

cores. J-Link Ultra raises the bar, aiming 

to be the fastest emulator available. 

J-Trace for Cortex-M for 

Post-Mortem Analysis 

J-Trace for ARM ® Cortex-M is a 

JTAG probe which includes trace (ETM) 

support. J-Trace assists the developer 

in analyzing his target system’s 

behavior. The 4 MB trace memory 

provides plenty of space to store the 

last executed functions. This allows you 

to find out how the program arrived at a 

certain position in code, which is either 

not expected or wanted. 


SEGGER: J-Link and Flasher 

Convenient development and production programming 

*The regular J-Link performs with an already high 

750 Kbps, J-Link Ultra allows an even faster peak 

download speed of 1.5 Mbps 

SEGGER Debug Probes and Production Flash Programmer 

J-Link 

Intelligent 

Debugging via 

JTAG/SWD 

• Robust communication 

• Very high performance 

(download speed up to 1.5 MB)* 

• Unlimited flash breakpoints 

(license required) 

Flasher for Production Flash 

Programming and in the Field 

Services 

The in-circuit programmer (Flasher 

ARM) is a superset of the J-Link DDL. 

It contains all of the debug probe 

features, while being designed for use 

in a production environment. Different 

interfaces, like the command line 

interface or the optionally available 

SDK, allow an easy integration into any 

production environment. 

The Flasher ARM has on-board 

memory to store your binary image, 

permitting simple stand-alone flash 

programming. This is particularly useful 

for support teams that have to upgrade 

devices out in the field. They only need 

to carry a small box which is readily 

configured to perform the update once 

it is connected to the target system. 

For more details, visit segger.com/ 

flasherarm.html.


SEGGER offers a feature rich, high 

performance RTOS, GUI, and family 

of middleware (file system, USB host 

and device, IP stack), all of which 

adhere to strict, yet efficient coding 

and documentation standards. The 

software is very easy to use and works 

out of the box. BSPs and projects for 

popular eval boards and tool chains are 

available, including BSPs for the popular 

Freescale based designs. SEGGER 

offers very flexible license models to 

meet any size project’s needs. 

Embedded Graphics 

Package (emWin) 

emWin is a professional graphical 

user interface (GUI) for any application 

that operates with a graphical LCD. 

For fast user interface development 

emWin provides a GUI-Builder software 

and an extensive widget selection. 

emWin is part of SEGGER’s complete 

middleware solution. Additionally, 

emWin is compatible with; polled, 

single-task, and multitask environments, 

with a proprietary operating system 

or with any commercial RTOS. It is 

shipped as C source code and may 

be adapted to any size physical and 

virtual display with any LCD controller 

and CPU. emWin can be optimized to 

run on very low resources. For more 

details, visit segger.com/emwin.html. 

RTOS (embOS) 

embOS is a priority-controlled real time 

operating system, designed to be used 

as a foundation for the development 

of embedded real-time applications. 

It is a zero interrupt latency (high 

priority interrupts are never disabled 

by embOS), high-performance RTOS 

that has been optimized for minimum 

memory consumption in both RAM 


and ROM, as well as high speed and 

versatility. Throughout the development 

process of embOS, the limited 

resources of MCUs have always been 

kept in mind. The internal structure 

of embOS has been optimized for 

a variety of applications for different 

customers, to fit the needs of different 

industries. embOS is fully sourcecompatible 

on different platforms 

(8/16/32-bit), making it easy to port 

applications to different CPUs. Its’ 

highly modular structure ensures that 

only those functions that are needed 

are linked, keeping the ROM size very 

small. We took full advantage of our 

partnership with Freescale by utilizing 

their expertise and knowledge of their 

hardware while adding support for 

Vybrid devices. This permits you to take 

full advantage of our software offering 

while being assured that it has been 

developed to the highest standards 

and optimized to the fullest. For more 

details, visit segger.com/embos.html. 

Embedded USB Stacks 

(emUSB-Device and 

emUSB-Host) 

emUSB-Device has been designed to 

work on any embedded system with a 

USB device controller. Ports for most 


SEGGER: RTOS, GUI and Middleware 

Embedded software for the professional developer 

SEGGER RTOS, GUI and Middleware 

common USB devices are available. It 

can be used with USB 1.1.or USB 2.0 

Full- and High-Speed devices. emUSB 

supports, among others, the HID, 

CDC, MSD, MSD-CDROM, printer and 

custom bulk communication classes. 

emUSB-Host is the counterpart of 

emUSB-Device and supports HID, 

CDC (and FTDI), MSD, printer and 

custom bulk communication classes. 

Embedded IP Stack 

(embOS/IP) 

embOS/IP is a TCP/IP stack that 

provides a small memory footprint 

for high-performance embedded 

networking solutions. The stack has 

been optimized for use in real-time, 

memory-constrained embedded 

systems. It offers RFC-compliant TCP/ 

IP and a standard socket API. embOS/ 

IP works seamlessly with the embOS 

operating system. Additional higher 

level protocols like SMTP, FTP and 

HTTP are also available. On the link 

layer, embOS/IP supports PPP to ease 

the integration of M2M-communication. 

For more details, visit segger.com/ 

embedded-software.html. 

61


Lauterbach 

TRACE32 ® 

PowerTools 

Lauterbach offers the world’s most 

advanced and complete debug 

environment. With more than 30 

years of experience, Lauterbach’s 

TRACE32 ® product line has 

accumulated an arsenal of analysis 

tools suitable for most debug and 

testing requirements. These tools 

range from traditional source code 

debug to statistical analysis, code 

coverage, charting and profiling of 

your code execution. 

With much experience supporting 

the various ARM ® core architectures, 

including ARM Cortex-A, ARM 

Cortex-R, ARM Cortex-M, 

and other Coresight components, 

Lauterbach is proud to announce 

support for the latest ARM 

Cortex-M4/Cortex-A5 based 

Freescale Vybrid devices. Offering a 

4-bit ETM trace port, the Vybrid part 

unleashes many of the advanced 

analysis features offered by the 

Lauterbach TRACE32 debugger, at 

a reasonable price point. There are 

several levels of debugger support, with 

or without support for the ETM trace. 

TRACE32 ® Debugger 

for ARM Cortex-M or 

ARM Cortex-A/R 

The tools for the ARM Cortex-M/ 

Cortex-A/R processor family 

are designed as an open debug 

environment that offers sophisticated 

features for quick and effective testing 

of your embedded design. It now 

supports the latest Freescale Vybrid 

devices with the ARM Cortex-M4/ 

Cortex-A5 core. 

62 

TRACE32 Debugger 

Hardware Configuration 

The PowerDebug for the ARM 

Cortex-M processor family consists of: 

• A high-speed debug hardware 

module 

• A debug cable for the ARM Cortex-M 

or ARM Cortex-A/R devices 

A USB2.0 or Ethernet interface 

is provided as host interface to 

PC Windows, PC Linux ® or any 

workstation. 


TRACE32 ® Debugger for ARM Cortex-M or ARM Cortex-A/R 

JTAG Debugger Features 

• Supports JTAG, SWD and cJTAG 

• C and C++ support for all standard 

compilers 

• Full and intuitive support of the 

on-chip debug unit 

• RTOS awareness for all commonly 

available RTOS 

• Real-time memory access via DAP 

• Flash programming support 

• Multicore debugging


TRACE32 CombiProbe 

for ARM Cortex-M 

TRACE32 JTAG debuggers can 

be extended with the CombiProbe 

which adds 4-bit ETM real time trace 

capabilities to the debugger, enabling 

the industry’s finest code analysis and 

profiling tools. 

CombiProbe Hardware 

Configuration 

The CombiProbe PowerDebug for 

ARM Cortex-M processor family 

consists of: 

• High-speed debug hardware 

module 

• CombiProbe debug cable for 

recording the 4-bit ETM v3.x in 

continuous mode 

• License for ARM Cortex-M 

debugging 

A USB2.0 or Ethernet interface is 

provided as host interface to PC 

Windows, PC Linux or any work 

station. The product also includes 

CoreSight Single Wire Viewer. 

CombiProbe Features 

• Up to 128 MB trace entries 

• Trace port rates up to 200 Mbps 

• Real-time profiling 

• Long-time trace 

• Energy profiling 

• Re-debugging of all sampled 

program steps (CTS) 

• Trace filter and trigger 

• Run time analysis of functions and 

tasks 

• Code coverage and variable analysis 

• Multicore debugging 

TRACE32 PowerTrace 

for ARM Cortex-A/R or 

ARM Cortex-M 

TRACE32 JTAG debuggers can be 

extended with the PowerTrace which 

adds 4/8/16/32-bit ETM real-time 

trace capabilities to the debugger, 

enabling the industry’s finest code 


analysis and profiling tools.This 

configuration supports all modes of 

the ETM trace port. 

PowerTrace Hardware 

Configuration 

The PowerTrace for ARM Cortex-M 

processor family consists of: 

• High-speed debug hardware 

module 

• PowerTrace module for recording 

4/8/16/32-bit ETM real-time trace 

• Debug cable for Cortex-A/R or 

Cortex-M debugging 

A USB2.0 or Ethernet interface is 

provided as host interface to PC 

Windows, PC Linux or any workstation. 

PowerTrace Features 

• Up to 4 GB trace entries (also, 

streaming to host for recording 

longer run times) 


TRACE32 ® CombiProbe for ARM Cortex-M 

TRACE32 ® PowerTrace for ARM Cortex-A/R or ARM Cortex-M 

• Trace port rates up to 600 MHz at 

4/8/16/32-bit trace widths 

• Real-time profiling 

• Long-time trace 

• Energy profiling 

• Re-debugging of all sampled 

program steps (CTS) 

• Trace filter and trigger 

• Run time analysis of functions and 

tasks 

• Code coverage and variable analysis 

• Multicore debugging 

For more information about TRACE32 

tools, visit lauterbach.com. 

63

For more information, visit freescale.com/Vybrid 

Freescale, the Freescale logo, CodeWarrior, ColdFire, Kinetis, PowerQUICC and Qorivva are trademarks of 

Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. Processor Expert, Vybrid and Xtrinsic are trademarks 

of Freescale Semiconductor, Inc. ARM is the registered trademark of ARM Limited. ARM9, ARM11, ARM Cortex-A5, 

ARM Cortex-A9, ARM Cortex-M3 and ARM Cortex-M4 are trademarks of ARM Limited. Java and all other Java-based 

marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The Power 

Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and 

service marks licensed by Power.org. All other product or service names are the property of their respective owners. 

© 2012 Freescale Semiconductor, Inc. 

Document Number: VYBRIDBYNDBITS REV 0

Beyond Bits VII - Freescale Semiconductor

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