Beyond Bits VII - Freescale Semiconductor

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Technical Highlights on-chip RAM, display controller units, OpenVG graphics processing unit, Quad SPI interfaces to external flash memories and available RTOS. All these components combine to provide a low system cost BOM because DRAM is not required. Target applications for single-core ARM Cortex-M4/Cortex-A5 MPU devices in the multi-market, general embedded space include asset tracking devices, 2D scanners, point-of-sale terminals, networked audio and data acquisition. In the industrial space, a single-core ARM Cortex-A5 MPU is targeted at industrial control, gas pumps and building control applications. Medical applications include patient monitoring and drug delivery mechanisms. A common theme in developing a dual-core architecture for these market segments is the inherent issues associated with a high-performance single (applications) processor running a high-level operating system coupled with the need for good real-time control. Vybrid devices address this growing number of consumer and industrial embedded applications that need higher application performance plus real-time responsiveness with its dual-core architecture combining the ARM Cortex-A5 application processor and the ARM Cortex-M4 for real-time control. This approach offers considerable flexibility in partitioning the software architecture across the dual-core hardware resources and provides options for reducing the RunIDD current consumption. It also removes the need for system designers to specify a higher performance single processor device in an effort to “oversample” the real-time events, thereby reducing system cost and power dissipation. 20 Vybrid Core Architecture Summary Comparison A “processor-centric” high-level Vybrid device block diagram is presented in the previous figure. The basic microarchitecture includes the dual-core structure interfacing to the network interconnect system bus fabric, providing the hardware interconnect matrix and supporting a 64-bit third-generation ARM-AMBA Advanced eXtensible Interface split transaction protocol. This is followed Back to Table of Contents Vybrid Key Architecture Features ARM ® Cortex-A5 ARM Cortex-M4 Instruction set architecture ARMv7-A ARMv7-ME, +-M4F (FPU) Architecture width 32 bits 32 bits Operating frequency relative to platform (2,3) x platform MHz 1x platform MHz Integer performance Microarchitecture 1.57 DMIPS 2.1 per MHz 1.25 DMIPS 2.1 per MHz • Pipeline Eight stages Three stages • Instruction issue Limited superscalar (ALU + Br) Single • Execution units L1 processor, local memories • Capacity, organization VFPv3 (SP + DP FPU) NEON SIMD MMU, TrustZone I-Cache, D-Cache I-Cache = 32 KB, 2-way SA D-Cache = 32 KB, 4-way SA 32 byte cache line size (4 beat, 64-bit burst) SPFPU v7-ME (DSP + SIMD) CodeCache, SystemCache, TCM (Lower, Upper) CodeCache = 16 KB, 2-way SA SystemCache = 32 KB, 2-way SA 32 byte cache line size (4 beat, 64-bit burst) TCML(ower) = 32 KB TCMU(pper) = 32 KB Accesses from other masters via backdoor port L2 processor memories Optional L2 Cache • Capacity, organization L2-Cache = 512 KB, 8-way SA 32 byte cache line size, (4 beat, 64-bit burst) System bus interface 1x 64-bit AMBA3 AXI 2x 64-bit AMBA2 AHB-Lite On-chip RAM (OCRAM) Three 64-bit AXI ported memory controllers + arrays, 1.5 MB total • 2x system RAM (_sys) controllers, each 256 KB in capacity, 512 KB total Optionally includes single-bit correction, double-bit detection (SECDED) ECC • 1x Graphics RAM (_gfx) Controller, 1 MB total 512 Kbytes optionally used as L2 cache data array Programmable support for on-the-fly conversion of 16-bit pixel data to/from 32-bit ARGB8888 DDR DRAM controller 2x 64-bit AXI input ports and 16-bit external DDR data bus Quad SPI memory controller 2x Quad SPI external memory controller FlexBus memory controller Gluelessly interfaces to external (non-DRAM) memories and/or ASICs, six chip selects by connections to a full complement of on-chip memories and slave peripherals connected via peripheral bridges as well as memory controllers for external interfaces including a multi-ported DDR DRAM controller, dual Quad SPIs and a FlexBus controller for glueless interfaces to simple (non-DRAM) memories and/or ASIC devices.
Back to Table of Contents ARM ® Cortex-A5 Processor Pipeline Organization 1 Fetch 1 Fetch 2 Fetch 3 ARM ® Cortex-M3 and ARM Cortex-M4 Pipeline For the standard configuration, Vybrid systems can best be characterized as a heterogeneous, symmetric, cachebased dual-core MPU architecture. The two ARM Cortex cores share an instruction set architecture with a common memory map, and the freescale.com/Vybrid Instruction ruc Queue ue Decode 1 “ARM’s Midsize Multiprocessor, Next Cortex-A5 Supports Four-Way Coherent Multiprocessing,” Tom R. Halfhill, Microprocessor Report, 10/26/2009 LSU branch result Fe De Ex Fetch Address Generation Unit Instruction Decode and Register Read Branch Address Phase and Writeback Shift Multiply and Divide Branch Forwarding and Speculation LU Branch No Forwarded/Speculated Issue Addr Gen Data Phase Load/ Store and Branch ALU and Branch LSU Branch Result Mul1 Shift Delta Cache 1 FP1 address space is effectively accessible from either core. Memory coherency is wholly managed by software. There is hardware support for basic multicore requirements including peripheral interrupt steering plus directed CPU interrupts for inter-processor Beyond Bits Vybrid Edition WR Mul2 ALU Delta Cache 2 FP2 Writeback Writeback Writeback FP3 FP4 FP5 communication, semaphores, run/ halt/reset control, memory protection via ARM’s TrustZone architecture with Freescale security extensions and shared dual-core debug resources including cross-triggering capabilities. With significant amounts of both processor-local memories (L1 core caches, ARM Cortex-M4’s tightly coupled memories with its backdoor port for alternate bus master accesses, and the optional ARM Cortex-A5 512 KB L2 cache) and the SoC resources associated with on-chip RAM and boot ROM plus the controllers for the external DDR DRAM, Quad SPI (flash) memories and FlexBus, the Vybrid architecture is a high-performance dual-core implementation, providing rich applications in real time for a number of growing embedded application spaces. 21
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