Beyond Bits VII - Freescale Semiconductor
Beyond Bits VII - Freescale Semiconductor
Beyond Bits VII - Freescale Semiconductor
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Core Technology<br />
ARM ® Cortex-A5 and ARM Cortex-M4 processors<br />
In developing a new generation, 40 nm<br />
integrated 32-bit family, <strong>Freescale</strong><br />
defined a dual-core architecture,<br />
combining the best features of the<br />
industry-standard ARM ® Cortex-A5<br />
application processor with the realtime<br />
focus of an ARM Cortex-M4<br />
control processor. Indeed, the 32-bit<br />
Vybrid family provides rich application<br />
capabilities with real-time control<br />
because each core has unique<br />
freescale.com/Vybrid<br />
attributes that make it the appropriate<br />
choice for specific embedded<br />
application spaces. The Vybrid family<br />
is ideally suited for automotive,<br />
industrial and general embedded<br />
applications. This solution is highly<br />
integrated, reducing system cost for<br />
the target applications. It includes<br />
a number of advanced architectural<br />
features so it can support either MCU<br />
or MPU configurations.<br />
Vybrid Processor Cores and Slave Memories Block Diagram<br />
Tag 7<br />
(Optional)<br />
Tag 0<br />
0<br />
1<br />
Data<br />
7<br />
RAM<br />
Array, 32K<br />
Tag/Data<br />
Arrays, 2x 8K<br />
The processor architecture can also<br />
be configured as a uniprocessor with<br />
either the ARM Cortex-A5 or the ARM<br />
Cortex-M4 as the operating core.<br />
For markets needing a single-core<br />
applications processor in the ARM<br />
Cortex family, the ARM Cortex-A5 is<br />
the best “value” application processor<br />
(in terms of MIPS/mW). Other key<br />
device components include a large<br />
ARM<br />
TPIU<br />
CTI<br />
DAP<br />
® Cortex-A5 Core Complex ARM ® Cortex Core Complex<br />
Debug (ITM, ETM, ETB, CTI)<br />
FPU + NEON<br />
NVIC FPU<br />
CM4 CPU<br />
FPB<br />
DWT<br />
Mul<br />
Inst<br />
ALU/Shift Q<br />
Ld/St<br />
PFU and Branch Predictor<br />
AP Bus Matrix ITM<br />
SystemBus CodeBus<br />
Data uTLB Inst uTLB<br />
TCMU<br />
TCML<br />
STB<br />
D-$<br />
TLB<br />
4 x 8K<br />
AXI BIU<br />
L2 Cache Controller<br />
AXI System Bus<br />
64<br />
DDRC Quad SPI<br />
I-$<br />
2 x 16K<br />
OCRAM<br />
_sys<br />
NIC-301<br />
OCRAM<br />
_sys<br />
OCRAM<br />
_gfx<br />
Boot<br />
ROM<br />
Sys-$<br />
AHB System Bus<br />
Sys<br />
BIU<br />
Code<br />
BIU<br />
FlexBus PBRIDGE<br />
Code-$<br />
Technical Highlights<br />
RAM<br />
Array, 32K<br />
Tag/Data<br />
Arrays, 2x 8K<br />
64 64<br />
64<br />
AHS Code Bus AHB Backdoor Port<br />
19
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