Beyond Bits VII - Freescale Semiconductor

Technical Highlights
Features
• Complies with USB specification
rev 2.0
• USB host mode
Supports EHCI
34
Supports HS operation using
internal on-chip HS PHY
Supported by Linux ® and other
commercially available operating
systems
• USB device mode
Supports HS operation using
internal on-chip HS PHY
Supports FS/LS operation using
internal HS PHY
Supports one upstream facing
port
Supports six programmable,
bi-directional USB endpoints,
including endpoint 0
• Suspend mode/low-power
As host, firmware can suspend
individual devices or the entire
USB and disable
Chip clocks for low-power
operation
Device supports low-power
suspend
Remote wakeup supported for
host and device
Integrated with processor doze
and stop modes for low-power
operation
Start of Frame
USB audio use cases require some
sort of audio clock recovery capability.
The Vybrid system USB OTG controller
supports use of the start of frame
(SOF) signal, which is generated at
the start of a microframe in the USB
2.0 HS protocol. This is a signal with
a rate of 125 microseconds. When
operating in full-speed mode, the SOF
SOF Implementation on the Vybrid Platform
USB OTG 0
USB OTG 1
USB0 SOF
USB1 SOF
signal has a rate of 1 ms pulse that
asserts for 64 system clock cycles
when the SOF token is detected on
the USB bus and the USB controller is
in device mode.
In order to properly support USB audio
isochronous asynchronous mode of
operation, it is necessary to measure
how many audio sample clock ticks
occur between two consecutive
occurrences of the SOF signal. This
measurement is used to provide
feedback to the USB audio source in
order to speed up or slow down the
audio sample delivery over the USB
bus.
This is the method of estimating the
ratio between the USB host clock
(SOF occurrences) and the Vybrid
device local audio clock.
The figure above shows the USB SOF
connectivity with FlexTimer to enable
this scheme.
FTM0
FTM1
FTM2
FTM3
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64 Cycles
Pulse
Stretcher
64 Cycles
Pulse
Stretcher
1. The two SOF signals (one from each USB port) must be brought to two timer
channels of one FlexTimer. This flexibility is provided in FTM2 and FTM3 as
shown in figure.
2. At least one of the SOF should be connected to one channel of a second
FlexTimer. This will allow measuring of two sets of audio clock/SOF signals.
To accommodate this, the USB0 SOF is connected to all FlexTimers.
USB OTG/HOST PHY
Architecture
USB0 SOF_PULSE
USB1 SOF_PULSE
Audio Master Clock should also be provided as one of the clock options to FlexTimers.
The USB OTG HS PHY is a HS/FS/
LS USB 2.0 PHY, integrated with the
controller.
The USB OTG HS HY comprises two
USB 2.0 transceiver sub-modules, one
OTG sub-module and one common
module shared between USB OTG
and USB H1 channels.
USB OTG PHY Features
• Complete physical interface module
for USB 2.0 On-the-Go
• UMTI+ Level 3 specification compliant
• Supports USB HS (480 Mbps), FS
(12 Mbps) and LS (1.5 Mbps)
• Host, slave and OTG dual role device
operational modes of OTG port
• Host modes of host port
• Integrated self-calibrated
termination resistors for HS mode
and full set of pull-up/pull-down
resistors defined by USB 2.0
electrical requirements