Beyond Bits VII - Freescale Semiconductor

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Technical Highlights • Interrupt-driven operation with seven ISO-7816 specific interrupts: Wait time violated 40 Character wait time violated Block wait time violated Initial character detected Transmit error threshold exceeded Receive error threshold exceeded Guard time violated Variety of Communications Formats Available The UART offers a number of options for data size, format and transmission/ reception settings. The variety of available options makes the UART capable of implementing a wide variety of serial communications protocols. Features • Eight- and nine-bit data formats supporting parity over all nine bits • MSB or LSB first on wire • Programmable transmitter output polarity • Programmable receiver input polarity FIFOs with DMA Request Capability The UART FIFOs reduce the frequency of CPU processing required by the UART. The DMA can be configured to transfer an entire packet of data and then interrupt the CPU when all bytes are received. This means the CPU can process the entire packet all at once instead of needing to stop the current program flow to move data bytes as they are received. The size of the FIFOs vary depending on the particular device and the specific UART. The Vybrid platform supports 16-byte FIFO on two UARTS (UART0 and UART1) and 8-byte FIFO on the other UARTS (UART2, UART3, UART4, UART5). UART UART Receive Receive Logic Logic Module Clock RxD LOOPS RSRC From Transmitter RxD SBR12:0 BRFA4:0 RE RAF Baud Rate Generator Receive Control Receiver Source Control Active Edge Detect UART UART Data Data Formats Formats Infrared Logic Eight Bits of Data with LSB First START BIT BIT 0 Internal Bus Stop Data Buffer Variable 12-bit Receive Shift Register Shift Direction PE Parity PT Logic Back to Table of Contents Start Wakeup Logic 7816 Logic IRQ/DMA Logic BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 ADDRESS MARK BIT 7 STOP BIT Eight Bits of Data with MSB First ADDRESS MARK START BIT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 M M10 LBKDE MSBF RXINV DMA Requests IRQ Requests To TxD START BIT Nine Bits of Data with LSB First ADDRESS MARK START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP BIT Nine Bits of Data with MSB First ADDRESS MARK START BIT BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 STOP BIT BIT 0 START BIT STOP BIT START BIT START BIT
Software and Development Tools
Page 1: BeyondBits Issue 7 VYBRID EDITION R
Page 4 and 5: Vybrid Family Overview 4 Vybrid Con
Page 6 and 7: Vybrid Controller Solutions Vybrid
Page 8 and 9: Vybrid Family Back to Table of Cont
Page 20 and 21: Technical Highlights
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Page 24 and 25: Technical Highlights Multicore Comm
Page 26 and 27: Technical Highlights Multimedia Sub
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Page 30 and 31: Technical Highlights platform. HAB
Page 32 and 33: Technical Highlights Power Domains
Page 34 and 35: Technical Highlights 32 On-chip tra
Page 36 and 37: Technical Highlights Features • C
Page 38 and 39: Technical Highlights Vybrid DRAM Co
Page 40 and 41: Technical Highlights FlexBus The Fl
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Beyond Bits VII - Freescale Semiconductor

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