Beyond Bits VII - Freescale Semiconductor

Vybrid Family
Back to Table of Contents
Vybrid VF6xx Family
Dual heterogeneous core solution with XGA display, dual USB,
dual Ethernet and L2 switch for automation and HMI
The VF6xx is the
heterogeneous dualcore
family combining the
ARM ® Cortex-A5 and
Cortex-M4 cores.
It includes dual USB 2.0 OTG
controllers with integrated
PHY, dual 10/100 Ethernet
controllers with L2 switch,
1 MB of on-chip SRAM and a
rich suite of communication,
connectivity and humanmachine
interfaces (HMI).
Target Applications
• Industrial automation
• Health care systems
• Multi-lane point-of-sale
• Buildling control
Mixed-Signal Capability
• Two 12-bit ADCs with configurable
resolution. Single or differential
output mode operation for improved
noise rejection. 500 ns conversion
time achievable with programmable
delay block triggering
• Two 12-bit DACs for analog
waveform generation for audio
applications or sensor manipulation
Memory
• Dual Quad SPI supporting a double
data rate interface, an enhanced read
data buffering scheme, Executein-Place
and support for dual-die
flashes
• Boot ROM with optional high
assurance boot for secure booting
capability
14
Vybrid VF6xx Family
Vybrid V600 Block Diagram
Debug and Trace
JTAG
Trace
Timers
FlexTimer (8-ch.)
FlexTimer (2-ch.)
FlexTimer (2-ch.)
FlexTimer (8-ch.)
IEEE ® 1588 Timers
Periodic Interrupt Timers
Low Power Timers
Memory
Boot ROM
1 MB SRAM
Memory Interfaces
DDR Controller
NAND Flash Controller
Quad SPI x2
External Bus Interface
• Up to 1 MB on-chip SRAM with
ECC support on 512 KB
• 16-bit DDR controller with PHY and
ECC support capable of DDR3/
LPDDR2 800 MHz data rate
Performance
Core
ARM ® Cortex-A5
Up to 500 MHz
DP-FPU
NEON
L1 I/D-Cache
L2 Cache
Trace/Debug
GIC
• ARM Cortex-A5 core with frequency
up to 500 MHz, with 32 KB each
instruction and data L1 cache
and 512 KB L2 cache double
precision floating point, NEON media
processing engine for acceleration
of media and signal processing, and
TrustZone security extension
• ARM Cortex-M4 core running
up to 167 MHz, with 16 KB of
instruction/data L1 cache plus 64
KB of tightly coupled memory,
DSP support for single cycle
32-bit MAC, single instruction
System
AMBA NIC
Internal and
External Watchdog
Interrupt
Router
DMA
Up to 64-ch.
Power
Management
Regulators
Memory
Protection
Unit
Core
ARM ® Cortex-M4
Up to 167 MHz
SP-FPU
DSP
Trace/Debug
I/D-Cache
NVIC
Display Security
TFT LCD
Crypytography Module
Touch Screen Controller
Tamper Detect
Video
Video Interface w/Camera
Secure RTC
OpenVG GPU
Secure RTIC
Audio
Secure RAM
ASRC
Secure Fuses
SAI x4
ESAI
Secure WDOG
SPDIF
Secure JTAG
multiple data extensions and single
precision floating point unit
• Up to 64-channel DMA for
peripheral and memory servicing
with reduced CPU loading and
faster system throughput
• Crossbar switch enables concurrent
multi-master bus accesses,
increasing bus bandwidth
Timing and Control
Analog
12-bit ADC x2
12-bit DAC x2
PLL
Clocks
Clock
Monitors
Internal Reference
Clocks
Low/High Frequency
Oscillators
Communication
UART x6 CAN x2
DSPI x4 I
IEEE 1588
Ethernet x2
L2Switch
USB Host + PHY
LS/FS/HS
USB OTG + PHY
LS/FS/HS
Secure Digital x2
141 GPIO
(with Interrupt)
2C x4
• Four flex timers with a total of 20
channels. Hardware dead-time
insertion and quadrature decoding
for motor control
• Four-channel 32-bit periodic
interrupt timer provides time base
for RTOS task scheduler or trigger
source for ADC conversion and
programmable delay block