Beyond Bits VII - Freescale Semiconductor

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Technical Highlights platform. HAB supports booting the device to a known initial state by using digital signatures to recognize authentic software and running software signed by the device manufacturer. In addition, HAB can protect the confidentiality of software during off-chip storage by decrypting the software loaded into RAM prior to execution. The figure to the right shows HAB encrypted boot supported on the Vybrid platform. The software image is encrypted using a secret key before being programmed on the off-chip memory (typically flash). During boot, HAB uses the same secret key (stored in hardware fuses not visible to the user) to decrypt the software image. Hardware Security Elements Vybrid platform security architecture includes the following hardware components: • Cryptography acceleration and assurance module Supports acceleration and off-loading for selected crypto algorithms Supports NIST SP800-90 compliant hardware random number generator 16K secure memory (automatic zeroization) with up to four independent partitions Supports AES, DES, 3 DES, ArcFour Symmetric key blog ciphers Supports MD5, SHA-1, SHA-224, SHA-256 hashing algorithms • Random number generation NIST compliant SP800-90 Combination of a true random number generator and a pseudo-random number generator 28 Encrypted High Assurance Boot Encryption Using Secret Key SW Image Encrypt (AES) Encrypted SW Image Build Environment Device Boot Secret Key Manufacturing OTP Key CAAM (AES) • Real-time integrity checker Periodic check on system memory for unauthorized modifications Supports up to four memory regions Use SHA-1 or SHA-256 as hashing algorithm Once started, RTIC can only be stopped and restarted by trusted software • Secure non-volatile storage Secure non-rollover real-time counter Non-rollover monotonic counter Zeroizable 256-bit secret key Support for tampers • Tamper Detection Support for up to six external tamper detectors Active tamper detection Wire mesh tamper Voltage, temperature and clock tamper detectors Key Blob Flash OTP Key Back to Table of Contents Secret Key Decrypt (AES) Key Blob Decryption Using Secret Key Decrypted SW Image Decrypt (AES) Encrypted SW Image • TrustZone Address Space Controller Supports 2, 4, 8 or 16 independent address regions Access controls are independently programmable for each address region Protects all AXI slave memories—DDR, on-chip SRAM All AHB slave memories, FlexBus, Quad SPI are protected by AHB equivalent address space controller • Other security sub-blocks Secure fuses (OTPs) Central security unit AHB TrustZone Controller Trust Zone Watchdog Secure JTAG Controller
Back to Table of Contents Power Management Programmable power options for performance and long battery life The Vybrid platform was designed with power efficiency as one of its main goals. To reduce current consumption, the design has: • Dynamic power management of core and peripherals • Software-controlled clock gating of peripherals • Multiple power domains and voltage scaling to minimize leakage in lowpower modes Vybrid devices have a power management unit supporting a variety of operating modes to optimize SoC/ application power consumption. There are nine modes of operation to allow the user to optimize power consumption for the level of functionality needed as well as several wakeup sources for the power modes. A low-leakage wakeup unit has up to eight internal peripheral wake-up sources, as well as up to sixteen external pins for wakeups. Several wakeup sources are available in the lowest power mode: low-power timer, real-time clock, ADC, DAC and several pin interrupts. Depending on the requirements of the user application, a variety of stop modes are available that provide state retention, partial power down and/or full power down of certain logic and/or memory. I/O states are held in all modes of operation except power gated modes (LPSTOP1, LPSTOP2, LPSTOP3). I/O state for 16 wakeup pads is still retained in power gated modes. freescale.com/Vybrid Modes of Operation Modes General Description General Description Normal Normal Recovery Recovery Method Method RUN RUN All functionality of Faraday is available All functionality of Vybrid platform is available N/A N/A WAIT CA5 and CA5 CM4 and cores CM4 Halted cores halted Interrupt Interrupt LPRUN 24MHz 24 operation, MHz operation, PLL Bypass PLL bypass Interrupt Interrupt ULPRUN ULPRUN STOP STOP LPSTOP3 32/128 kHz operation, PLL off Interrupt 32kHz /128kHz operation, PLL Off Interrupt Lowest power mode with all power retained, Lowest power mode with all power retained, RAM Interrupt RAM retention and LVD protection Interrupt retention and LVD protection 64K RAM retention. I/O states held. 64K (tbd) ADCs/DACs RAM retention. optionally I/O states held. ADCs/DACs Wake-up/Reset FPO power-gated. RTC Wakeup/Reset optionally power-gated. RTC functional. Wakeup from interrupts functional. Wakeup from interrupts LPSTOP2 LPSTOP2 16K RAM retention. I/O states held. 16K (tbd) RAM retention. I/O states held. ADCs/DACs optionally ADCs/DACs power-gated. optionally RTC functional. power-gated. Wakeup from RTC interrupts functional. Wakeup from interrupts Wake-up/Reset Wakeup/Reset LPSTOP1 I/O states I/O states held. ADCs/DACs held. ADCs/DACs optionally powergated. optionally RTC Wake-up/Reset LPSTOP1 functional. powergated. Wakeup from RTC interrupts functional. Wakeup from Wakeup/Reset Battery All supplies interrupts OFF, SRTC, 32kXOSC ON, tampers and monitors POR Backup ON. All supplies OFF, SRTC, 32k XOSC ON, Battery Backup tampers and monitors ON. POR LPRUN and ULPRUN are part of RUN Mode and there are no separate modes. Features • Single 3.3V+/-10% supply voltage • High-power voltage regulator with an external ballast transistor generating internal 1.2V supply voltage, 1.2A capacity and quiescent current less than 1 mA • Ability to switch supply voltage down from 1.2 to 1.1V in lowpower modes to minimize power consumption • Soft start of main high-power regulator to minimize in-rush currents. Start-up time < 500 us • Low-power regulator: For Stop modes. 50 mA capacity and quiescent current < 50 uA <strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition • Ultra-low power regulator: For LPStop modes. 10 mA capacity and quiescent current < 5 uA • Well bias generator to increase well by ~300mV to minimize leakage in low-power modes • Multiple power domains and power gating to minimize low-power consumption • Low voltage detection (LVD) on main supplies and 1.2V supplies • 16 wakeup pins for low-power wakeup • The single 3.3V supply is used in the system for I/O power with the exception of the DRAM interface. The DRAM interface power will be generated external to the Vybrid SoC 29
Page 1: BeyondBits Issue 7 VYBRID EDITION R
Page 4 and 5: Vybrid Family Overview 4 Vybrid Con
Page 6 and 7: Vybrid Controller Solutions Vybrid
Page 8 and 9: Vybrid Family Back to Table of Cont
Page 20 and 21: Technical Highlights
Page 22 and 23: Technical Highlights on-chip RAM, d
Page 24 and 25: Technical Highlights Multicore Comm
Page 26 and 27: Technical Highlights Multimedia Sub
Page 28 and 29: Technical Highlights Enhanced Seria
Page 32 and 33: Technical Highlights Power Domains
Page 34 and 35: Technical Highlights 32 On-chip tra
Page 36 and 37: Technical Highlights Features • C
Page 38 and 39: Technical Highlights Vybrid DRAM Co
Page 40 and 41: Technical Highlights FlexBus The Fl
Page 42 and 43: Technical Highlights • Interrupt-
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Beyond Bits VII - Freescale Semiconductor

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