Beyond Bits VII - Freescale Semiconductor

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USB Subsystem
Flexible USB connectivity with integrated PHY
The USB subsystem in Vybrid devices
is comprised of several blocks
that together provide flexible USB
functionality. The USB subsystem
includes:
• Dual USB On-The-Go (OTG)
2.0 compliant controller (specific
controller depends on the device).
Options are: High-Speed (HS), Full-
Speed (FS) and Low-Speed (LS)
• Dual on-chip HS USB PHY
• USB regulator
USB Controller
The USB controller is a USB
2.0-compliant serial interface engine
for implementing a USB interface. The
USB controller provides USB host
and device communications along
with support for OTG operation. The
controller supports HS, (480 Mbps),
FS (12 Mbps) and LS (1.5 Mbps)
data transfer rates. The registers and
data structures are based on the
enhanced host controller interface
specification (EHCI) for USB standard.
The USB OTG module can act as a
host or device. The USB controller
is programmable to support host or
device operations under firmware
control. On-chip HS PHY is used
for the 60 MHz clock source to the
controller. The USB controller provides
control and status signals to interface
with external USB OTG and USB
host power devices. Customers can
use these control and status signals
on the chip interface and the I 2 C bus
to communicate with external USB
On-The-Go and USB host power
devices. USB host modules must
supply 500 mA with a 5V supply
on its downstream port (referred to
freescale.com/Vybrid
USB OTG/HOST PHY Architecture
BIAS
PLL
Common
Block
OTG
as VBUS), however, the USB OTG
standard provides a minimum 8 mA
VBUS supply requirement. If the
connected device attempts to draw
more than the allocated amount of
current, the USB host must disable the
port and remove power. USB VBUS is
not provided on-chip. The Vybrid SoC
provides pins for control and status to
an external IC capable of managing
the VBUS downstream supply.
Beyond Bits Vybrid Edition
HS/FS/LS
Receivers
Squelch/
Disconnect
Clock
Buffers
Receiver
Transmitter
Local Bias
D+/D- Pull-up/
Pull-down Logic
HS/FS/LS
Transmitters
Single-Ended
Receivers
Analog Block
HS/FS/LS
Receivers
Squelch/
Disconnect
Clock
Buffers
Receiver
Transmitter
Local Bias
D+/D- Pull-up/
Pull-down Logic
HS/FS/LS
Transmitters
Single-Ended
Receivers
Analog Block
Test
Interface
HS DLL
Elasticity
Buffer
FS DPLL
HS
FS
Transceiver
MUX
Test
Interface
HS DLL
Elasticity
Buffer
FS DPLL
HS
FS
Transceiver
MUX
SYNC
Detector
MUX
FS/LS
NRZI
Decoder
NRZI
Encoder
Bit
Unstuffer
Receive
State
Machine
Transmit
State
Machine
Bit
Stuffer
USB 1.1
Transceiver
FS/LS
Digital Block
SYNC
Detector
MUX
FS/LS
NRZI
Decoder
NRZI
Encoder
Bit
Unstuffer
Receive
State
Machine
Transmit
State
Machine
Bit
Stuffer
USB 1.1
Transceiver
FS/LS
Digital Block
Rx Shift
and Hold
Control
Logic
Tx Shift
and Hold
Rx Shift
and Hold
Control
Logic
Tx Shift
and Hold
For OTG operations, external circuitry
is required to manage the host
negotiation protocol (HNP) and session
request protocol (SRP). External ICs
that are capable of providing the OTG
VBUS with support for HNP and SRP,
as well as support for programmable
pull-up and pull-down resistors on the
USB DP and DM lines, are available
from various manufacturers.
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