Beyond Bits VII - Freescale Semiconductor
Beyond Bits VII - Freescale Semiconductor
Beyond Bits VII - Freescale Semiconductor
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<strong>Beyond</strong><strong>Bits</strong><br />
Issue 7<br />
VYBRID EDITION<br />
Rich applications<br />
in real time<br />
INTRODUCING<br />
Vybrid Controller<br />
Solutions<br />
March 2012
Introducing Vybrid<br />
Controller Solutions<br />
Rich applications in real time<br />
freescale.com/Vybrid<br />
Welcome to the latest edition of <strong>Beyond</strong> <strong>Bits</strong>, created to help you bring your innovative<br />
design ideas to life.<br />
This edition provides an in-depth look at our Vybrid portfolio of controller solutions, designed to dramatically<br />
simplify solutions that need rich human-machine interface (HMI) and connectivity concurrent with real-time<br />
control and response. We’re taking the concept of a total embedded solution approach further, and helping<br />
you bring differentiated products to market faster. Complex embedded systems must continue to operate<br />
consistently and predictably. The Vybrid brand is distinguished by software tightly coupled with silicon—<br />
enabling concurrent low-latency communication between high-level operating systems such as Linux and<br />
real-time operating systems (RTOS) like MQX. We realize that the majority of product development time<br />
lies in getting the software right. Starting with the Vybrid portfolio, we will release software virtual models of<br />
silicon to help you begin software development before silicon is available—shortening the cycle of time to<br />
revenue.<br />
The Vybrid family provides unprecedented system integration, starting with a unique heterogeneous<br />
architecture that brings together ARM ® Cortex-A and ARM Cortex-M cores as well as a powerful array<br />
of peripherals. Extensive communication and memory options, as well as support for external peripherals and<br />
memory, are available. Security and data integrity has been carefully considered, with features for safeguarding<br />
memory, content management and communication. HMI and multimedia options include audio interfaces,<br />
dual display controllers, video interface and OpenVG GPU for UI acceleration.<br />
The Vybrid portfolio also provides a broad offering of supporting resources, including reference designs,<br />
application notes, white papers, on-demand training, board support packages and middleware. We also<br />
provide a way to ease early software development by releasing a software virtual model, as well as IDE tool<br />
support such as our Eclipse-based CodeWarrior Development Studio with Processor Expert, ARM DS-5 and<br />
the modular Tower System development platform. This support, along with the vast resources of the ARM and<br />
open-source communities, will help simplify your design process and reduce your time to market.<br />
Our extensive range of 8-, 16- and 32-bit MCUs and MPUs offers solutions you can trust. You can count<br />
on us to deliver industry-leading vertical solutions, scalable product lines, intellectual property and process<br />
technology roadmaps, outstanding technical support, a robust ecosystem and<br />
a broad range of devices, available for a minimum of 10 years.*<br />
Thank you for considering <strong>Freescale</strong> solutions for your next-generation design. We look forward to<br />
working with you.<br />
Regards,<br />
Reza Kazerounian<br />
Senior Vice President and General Manager<br />
Automotive, Industrial and Multi-Market Solutions Group<br />
<strong>Freescale</strong> <strong>Semiconductor</strong><br />
*For Terms and Conditions and to obtain a list of available products, visit freescale.com/productlongevity.<br />
Vybrid Controller Solutions<br />
1
Vybrid Family Overview<br />
4 Vybrid Controller Solutions<br />
8 Vybrid VF3xx Family<br />
10 Vybrid VF4xx Family<br />
12 Vybrid VF5xx Family<br />
14 Vybrid VF6xx Family<br />
16 Vybrid VF7xx Family<br />
Technical Highlights<br />
19 Core Technology<br />
22 Multicore Communication<br />
24 Multimedia Subsystem<br />
27 Security Subsystem<br />
29 Power Management<br />
31 Ethernet Subsystem<br />
33 USB Subsystem<br />
35 Memory Subsystem<br />
39 Universal Asynchronous Receiver/Transmitter<br />
Software and Development Tools<br />
42 <strong>Freescale</strong> Virtual Hardware Platform<br />
44 <strong>Freescale</strong> MQX Software Solutions<br />
48 <strong>Freescale</strong> Tower System<br />
50 Swell PEG Product Line<br />
51 Timesys LinuxLink<br />
52 CodeWarrior Development Studio<br />
54 DS-5<br />
56 IAR Embedded Workbench<br />
58 Atollic<br />
59 Multilink and Cyclone<br />
60 SEGGER: J-Link and Flasher<br />
61 SEGGER: RTOS, GUI and Middleware<br />
62 Lauterbach<br />
Table of Contents
Vybrid Family of Products
Vybrid Controller Solutions<br />
Vybrid Controller Solutions<br />
A unique heterogeneous platform solution<br />
The increasing complexity and<br />
demands of embedded systems<br />
creates greater need for sophisticated<br />
human-machine interfaces (HMI)<br />
and multiple connectivity options<br />
with safe, secure and predictable<br />
operation. To concurrently provide<br />
rich HMI and real-time control means<br />
bringing together two very different<br />
system paradigms. For example, HMI<br />
computation focuses on efficiently<br />
processing pixels and displaying<br />
them on a screen, while guaranteed<br />
determinism requires highly<br />
predictable response times for tasks.<br />
A traditional systems-level solution for<br />
such divergent needs would combine<br />
different pieces of silicon, such as<br />
an applications MPU and a real-time<br />
MCU, on a board. It would also require<br />
developing software and a protocol to<br />
enable simultaneous communication<br />
between real-time control and rich<br />
HMI. Application developers face a<br />
tremendous challenge of seamlessly<br />
integrating these diverse technologies<br />
in a single system.<br />
Our Vybrid portfolio brings to market<br />
a unique, low-power system solution<br />
that provides customers a way to<br />
combine rich applications requiring<br />
high-resolution graphical displays<br />
and connectivity with real-time<br />
determinism. The Vybrid portfolio<br />
enables customers to create systems<br />
that concurrently run a high-level<br />
operating system such as Linux ®<br />
and a real-time operating system<br />
such as MQX on the same device.<br />
This, along with a communication<br />
API between the rich domain and the<br />
real-time domain and a tool chain<br />
4<br />
Vybrid Portfolio Key Attributes<br />
Total<br />
System<br />
Solution<br />
Optimal<br />
System<br />
Performance<br />
that eases debug of such systems,<br />
dramatically shortens customer time<br />
to revenue. The families in the Vybrid<br />
portfolio span entry-level products for<br />
customers who want to upgrade from<br />
the Kinetis MCU to devices with large<br />
on-chip SRAM up to highly integrated,<br />
heterogeneous dual-core solutions<br />
that can serve industrial and consumer<br />
markets.<br />
Each device in the Vybrid portfolio<br />
offers a rich suite of reference designs,<br />
app notes, board support packages<br />
and middleware for its market space.<br />
This, along with the vast resources<br />
Rich Apps in Real Time<br />
Unprecedented<br />
System<br />
Integration<br />
Low-Power<br />
Process<br />
of <strong>Freescale</strong>, ARM ® and open-source<br />
communities, will help customers<br />
to develop software solutions and<br />
support for their applications and<br />
dramatically reduce time to market.<br />
Scalable and Compatible<br />
across Multiple Cores<br />
Vybrid devices have a dual core<br />
architecture that combines the ARM<br />
Cortex-A5 application processor and<br />
the ARM Cortex-M4 for real-time<br />
control. The Vybrid portfolio is designed<br />
to be compatible with Kinetis MCUs<br />
featuring the ARM Cortex-M4 core and<br />
the i.MX6 series featuring the ARM<br />
Cortex-A9 core, while also providing
Back to Table of Contents <strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Vybrid Family Details<br />
Vybrid<br />
Families DDR<br />
VF7xx Family<br />
[Heterogenous Dual Core]<br />
ARM ® Cortex-A5 up to 500 MHz<br />
ARM Cortex-M4 up to 167 MHz<br />
364-pin MAPBGA<br />
VF6xx Family<br />
[Heterogenous Dual Core]<br />
ARM Cortex-A5 up to 500 MHz<br />
ARM Cortex-M4 up to 167 MHz<br />
364-pin MAPBGA<br />
VF5xx Family<br />
ARM Cortex-A5 up to 500 MHz<br />
364-pin MAPBGA<br />
VF4xx Family<br />
ARM Cortex-A5 up to 500 MHz<br />
364-pin MAPBGA<br />
VF3xx Family<br />
ARM Cortex-A5 up to 266 MHz<br />
176-pin LQFP<br />
freescale.com/Vybrid<br />
Camera Interface<br />
Video ADC<br />
Common Platform, Analog and Digital<br />
CRC and TZ Address<br />
12-bit ADC<br />
Space Controllers<br />
I 2 C 12-bit DAC<br />
Programmable<br />
Delay Block<br />
USB Host w/PHY<br />
USB OTG w/PHY<br />
Segment LCD<br />
TFT LCD (w/<br />
Touch Screen)<br />
Ethernet<br />
Controller<br />
L2 Switch<br />
Security (HAB,<br />
Tamper, Det.)<br />
External Bus<br />
Y 2<br />
1<br />
Y<br />
Y<br />
Secure JTAG<br />
Flash Controller Secure Fuses<br />
UARTs Timers<br />
Low-Voltage,<br />
Low-Power Multiple<br />
Operating Modes,<br />
Clock Gating<br />
(1.73V–3.6V)<br />
Secure RAM<br />
eSDHC<br />
DMA<br />
ESAI SRAM<br />
2<br />
2<br />
2<br />
Tools<br />
Packaged IDE<br />
Packaged OS<br />
and Multicore<br />
Communication API<br />
Application Software<br />
Ind. Protocols,<br />
Peripheral Drivers<br />
Broad Third-Party<br />
Ecosystem Support<br />
Y<br />
Y<br />
scalable devices that can address the<br />
needs of a market that demands critical<br />
safety and security, connectivity and<br />
rich HMI in the same piece of silicon.<br />
The Vybrid roadmap is built with this<br />
scalability and code compatibility in<br />
mind so that the performance of the<br />
device roadmap grows with customers‘<br />
needs long into the future.<br />
One of the key benefits of the Vybrid<br />
heterogeneous architecture that<br />
combines the ARM Cortex-A5 core<br />
with the ARM Cortex-M4 core is the<br />
partitioning of tasks based on their<br />
characteristics. For tasks that need<br />
predictable interrupt management,<br />
for example, a typical need for realtime<br />
applications, the Vybrid platform<br />
has the ARM Cortex-M4 core with<br />
a Nested Vector Interrupt Controller<br />
(NVIC) while allowing graphical<br />
applications and connectivity stacks<br />
to be run on the ARM Cortex-A5<br />
applications processor.<br />
Software can be segmented so that<br />
tasks that need predictable latencies<br />
can be run on the ARM Cortex-M4<br />
core and computer intensive processes<br />
run on the ARM Cortex-A5 core.<br />
Total System Solution<br />
Vybrid devices take a total system<br />
approach. Complementing the lowpower<br />
silicon is a reference Linux BSP,<br />
a full-featured MQX RTOS, reference<br />
MQX BSP and a processor-toprocessor<br />
communication API that lets<br />
customers partition their code between<br />
the ARM Cortex-A5 (e.g., running<br />
Linux) and ARM Cortex-M4 (e.g.,<br />
running MQX) to implement the lowest<br />
power solution for their application<br />
demands. In addition, customers<br />
have access to industry-leading IDE<br />
tool chains such as CodeWarrior<br />
with Processor Expert, ARM DS-5<br />
and IAR. A selection of connectivity,<br />
motor control, LCD, security stacks<br />
5
Vybrid Family Back to Table of Contents<br />
and drivers is also available. Vybrid<br />
devices are supported by <strong>Freescale</strong>’s<br />
Tower System, offering the flexibility<br />
to easily scale and expand customer<br />
designs based on market need. Tower<br />
Systems allow rapid prototyping in a<br />
development platform that maximizes<br />
hardware reuse and speeds time to<br />
market.<br />
Vybrid devices also accelerate time<br />
to market by providing a range of<br />
on-demand resources including<br />
reference designs, application notes,<br />
white papers and training to assist in<br />
implementing designs.<br />
Low-Power Process<br />
One of the critical foundational pieces<br />
of the Vybrid platform is its low-power<br />
process technology. The devices in this<br />
portfolio are fabricated in the 40 nm<br />
low-power process. The static leakage<br />
of the 40 nm LP process is 2x less<br />
than 65 nm and almost 3x less than 90<br />
nm. This enables more integration for a<br />
6<br />
Process Technology Node Comparison<br />
Technology Node<br />
90LP<br />
65LP 55LP 40LP<br />
Active Power Standby Power Speed<br />
given power envelope thus dissipating<br />
much less power for the same device.<br />
Unprecedented System<br />
Integration<br />
The Vybrid platform has an<br />
unprecedented level of system<br />
integration for a solution of its class.<br />
The centerpiece is the core complex<br />
featuring the ARM Cortex-A5 and<br />
ARM Cortex-M4 cores.<br />
ARM Cortex-A5 Core<br />
The ARM Cortex-A5 processor is a<br />
high-performance, low-power core<br />
with an L1 and L2 cache subsystem<br />
that provides full virtual memory<br />
capabilities, double precision floatingpoint<br />
unit (FPU) and the NEON media<br />
processing engine. It is intended<br />
as an upgrade for the ARM9 ® and<br />
ARM11 ® cores and is architecturally<br />
compatible with Cortex-A9. The<br />
ARM Cortex-A5 also has TrustZone ®<br />
Technology for creating secure<br />
applications.<br />
ARM Cortex-M4 Core<br />
The ARM Cortex-M4 core retains all the<br />
advantages of the ARM Cortex-M3<br />
core with an NVIC which gives<br />
deterministic interrupt handling capability<br />
demanded by real-time applications.<br />
The ARM Cortex-M4 adds digital signal<br />
processing capability in the form of<br />
DSP and SIMD instruction extensions,<br />
a single cycle MAC unit and single<br />
precision FPU. In addition, <strong>Freescale</strong><br />
has added a direct memory access<br />
(DMA) controller, crossbar switch, L1<br />
on-chip cache memories and tightly<br />
coupled memories (TCM) which<br />
maximize processor performance and<br />
bus bandwidth.<br />
Communication Interfaces<br />
Vybrid devices feature a number of<br />
connectivity peripherals, including<br />
dual USB 2.0 (Low-, Full- and High-<br />
Speed) device/host/On-The-Go<br />
with integrated PHYs, dual 10/100<br />
Ethernet with Layer 2 Ethernet<br />
switch with IEEE ® 1588 hardware<br />
time stamping and reduced media<br />
independent interface (RMII) support<br />
for real-time industrial control. Multiple<br />
serial interfaces include UARTs with<br />
support for ISO7816 SIM/smart cards,<br />
SPI and I 2 C, while dual CAN modules<br />
enable industrial network bridging.<br />
Support for External Peripherals<br />
and Memory<br />
In addition to having up to 1.5 MB<br />
of on-chip SRAM for speedy code<br />
and data execution, Vybrid devices<br />
can interface to a variety of external<br />
peripherals and memories for system<br />
expansion and data storage. Dual<br />
Quad SPI interfaces with eXecute-in-<br />
Place (XiP) support can interface with<br />
the latest flash memory to offer up to<br />
160 MB/s of throughput. This allows<br />
for a very powerful single-chip solution<br />
when the large DDR memory sizes<br />
are not required. A secure digital host<br />
controller supports SD, SDIO, MMC
Back to Table of Contents<br />
or CE-ATA cards for in-application<br />
software upgrades, media files or<br />
adding Wi-Fi ® support. For interfacing<br />
to external peripherals such as<br />
external SRAM, EEPROM and other<br />
peripherals, a FlexBus external bus<br />
interface is provided. NAND flash and<br />
DRAM controllers with ECC support<br />
allow connection to a wide variety of<br />
memory types for critical applications.<br />
Battery-backed RAM is critical for<br />
secure systems to store authentication<br />
keys; Vybrid devices provide 16 KB<br />
of secure RAM. The platform also<br />
provides 96 KB ROM used for high<br />
assurance boot (HAB).<br />
Multimedia Options<br />
The Vybrid platform offers a host<br />
of multimedia options enabling<br />
customers to run rich applications with<br />
real-time control.<br />
Audio<br />
Three different types of audio<br />
interfaces are supported: synchronous<br />
audio interface (SAI) for full-duplex<br />
audio transfer, enhanced serial audio<br />
interface (ESAI) that is also full duplex<br />
and adds support for interfacing with<br />
SPDIF transceivers and the Sony/<br />
Philips Digital Interface (SPDIF) for<br />
digital audio support.<br />
Display Controller<br />
Two independent display controller<br />
units (DCU) interface with TFT LCD<br />
displays. The DCU can drive LCD<br />
displays up to a resolution of XGA<br />
(1024x768). Also included is a<br />
segment LCD controller.<br />
Video Interface Unit (VIU)<br />
For image and vision capture, a VIU<br />
provides a 24-bit parallel interface for<br />
digital video. In addition, an optional<br />
video ADC will convert composite<br />
video into digital format.<br />
freescale.com/Vybrid<br />
OpenVG Graphics<br />
Processing Unit<br />
Vivante GC355 OpenVG graphics<br />
accelerator supporting OpenVG1.1<br />
can be used for UI acceleration.<br />
Reliability, Safety and Security<br />
Vybrid devices include a variety of<br />
data integrity and security hardware<br />
features for safeguarding memory,<br />
communication and system data.<br />
A cyclic redundancy check module<br />
is available for validating memory<br />
contents and communication<br />
data, while a memory protection<br />
unit provides data protection and<br />
increased software reliability. For<br />
failsafe applications, an independently<br />
clocked watchdog offers protection<br />
against runaway code. When it comes<br />
to security, a hardware encryption<br />
unit supports several encryption<br />
and hashing algorithms for program<br />
validation as well as authentication<br />
and securing data for transfer and<br />
storage. The system security module<br />
includes a unique chip identifier,<br />
secure key storage and a hardware<br />
tamper detection system. The tamper<br />
detection system has integrated<br />
sensors for voltage, frequency,<br />
temperature and external sensing for<br />
physical attack detection.<br />
Optimal System<br />
Performance<br />
Vybrid devices are ideal for modern<br />
industrial applications that require<br />
higher integration of communication<br />
and connectivity interfaces, as well as<br />
HMI and UI acceleration. Customers<br />
can easily take full advantage of all<br />
the integrated Vybrid features to<br />
create differentiated products by<br />
leveraging the provided reference<br />
board support packages (BSP) for<br />
high-level operating systems (such<br />
as Linux) and real-time operating<br />
systems (such as MQX), which<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
include libraries and media framework<br />
tuned to the silicon architecture.<br />
The combination of high-efficiency<br />
silicon design, low-leakage process<br />
technology and software tuned for<br />
the silicon architecture results in<br />
low power consumption, eliminating<br />
the need for a fan or heat sink and<br />
helping to lower overall system BOM<br />
cost. As an example, because the<br />
platform architecture partitions tasks<br />
between the applications processor<br />
and the deterministic MCU, the ARM<br />
Cortex-M4 core helps to improve<br />
efficiency in industrial motor control<br />
applications which can result in a<br />
reduced carbon footprint.<br />
Vybrid Product Families<br />
The first five Vybrid families for<br />
industrial and consumer applications<br />
are scheduled to sample in Q3<br />
of 2012 with production planned<br />
for late Q4 2012 and early 2013.<br />
Vybrid products are built around a<br />
common set of system, analog and<br />
digital IP blocks. The devices in each<br />
product family are distinguishable<br />
by their performance and peripheral<br />
capabilities as shown in the “Vybrid<br />
Family Details” table on page 5.<br />
7
Vybrid Family Back to Table of Contents<br />
Vybrid VF3xx Family<br />
Single-chip solution with dual XiP Quad SPI, dual Ethernet and<br />
L2 switch for appliances and energy control<br />
The VF3xx family is<br />
the entry point into the<br />
Vybrid portfolio and features<br />
the ARM ® Cortex-A5 core.<br />
It provides an efficient<br />
solution for an applications<br />
processor with 1.5 MB of<br />
on-chip SRAM and a rich<br />
suite of communication,<br />
connectivity and humanmachine<br />
interfaces (HMI).<br />
Target Applications<br />
• Home energy automation<br />
• Low-end appliances<br />
• Portable patient monitors<br />
• Metering data concentrators<br />
Mixed-Signal Capability<br />
• Two 12-bit ADCs with configurable<br />
resolution. Single or differential<br />
output mode operation for improved<br />
noise rejection. 500 ns conversion<br />
time achievable with programmable<br />
delay block triggering<br />
• Two 12-bit DACs for analog<br />
waveform generation for audio<br />
applications or sensor manipulation<br />
Memory<br />
• Dual Quad SPI supporting a double<br />
data rate interface, an enhanced<br />
read data buffering scheme,<br />
Execute-in-Place and support for<br />
dual-die flashes<br />
• Boot ROM with optional high<br />
assurance boot for secure booting<br />
capability<br />
• Up to 1.5 MB on-chip SRAM with<br />
ECC support on 512 KB<br />
8<br />
Vybrid VF3xx Family<br />
Vybrid V300 Block Diagram<br />
Debug and Trace<br />
JTAG<br />
Trace<br />
FlexTimer (8-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (2-ch.)<br />
IEEE ® Timers<br />
1588 Timers<br />
Periodic Interrupt Timers<br />
Low Power Timers<br />
Memory<br />
Boot ROM<br />
1 MB SRAM<br />
Memory Interfaces<br />
NAND Flash<br />
Controller<br />
Quad<br />
SPI x2<br />
External Bus<br />
Interface<br />
Performance<br />
System<br />
AMBA NIC<br />
Internal and<br />
External Watchdog<br />
Interrupt<br />
Router<br />
DMA<br />
Up to 64-ch.<br />
Power Management<br />
Regulators<br />
Memory Protection<br />
Unit<br />
• ARM Cortex-A5 core running at 266<br />
MHz, with double precision floating<br />
point, NEON media processing<br />
engine for acceleration of media and<br />
signal processing, and TrustZone<br />
security extensions. 32 KB each of<br />
instruction and data L1 cache and<br />
512 KB L2 cache for optimized<br />
bus bandwidth and on-chip SRAM<br />
execution performance<br />
• Up to 64-channel DMA for<br />
peripheral and memory servicing<br />
with reduced CPU loading and<br />
faster system throughput<br />
• Crossbar switch enables concurrent<br />
multi-master bus accesses,<br />
increasing bus bandwidth<br />
ARM ® Cortex-A5<br />
Up to 266 MHz<br />
Timing and Control<br />
• Three flex timers with a total of 12<br />
channels. Hardware dead-time<br />
insertion and quadrature decoding<br />
for motor control<br />
• Four-channel 32-bit periodic<br />
interrupt timer provides time base<br />
for RTOS task scheduler or trigger<br />
source for ADC conversion and<br />
programmable delay block<br />
HMI<br />
Core<br />
DP-FPU<br />
NEON<br />
L1 I/D-Cache<br />
L2 Cache<br />
Trace/Debug<br />
GIC<br />
Display Security<br />
TFT LCD<br />
Crypytography Module<br />
Segment LCD<br />
Touch Screen Controller<br />
Tamper Detect<br />
Secure RTC<br />
Video<br />
Video Interface w/Camera<br />
Secure RTIC<br />
Audio<br />
Secure RAM<br />
ASRC<br />
Secure Fuses<br />
SAI x3<br />
Secure WDOG<br />
ESAI<br />
Secure JTAG<br />
Analog<br />
12-bit ADC x2<br />
12-bit DAC x2<br />
PLL<br />
Clocks<br />
Clock<br />
Monitors<br />
Internal Reference<br />
Clocks<br />
Low/High Frequency<br />
Oscillators<br />
Communication<br />
UART x4 CAN x2<br />
DSPI x3 I<br />
IEEE 1588<br />
Ethernet x2<br />
L2 Switch<br />
USB OTG + PHY<br />
LS/FS/HS<br />
Secure Digital x1<br />
125 GPIO<br />
(with Interrupt)<br />
2C x2<br />
• TFT LCD display capable of<br />
WQVGA resolution<br />
• 288 segment LCD controller<br />
• Four-wire touch screen controller for<br />
resistive touch screens
Back to Table of Contents<br />
• Xtrinsic low-power touch-sensing<br />
interface with up to 16 inputs.<br />
Operates in all low-power modes.<br />
Hardware implementation avoids<br />
software polling method. High<br />
sensitivity level allows use of overlay<br />
surfaces up to 5 mm thick<br />
Multimedia<br />
• Video interface unit with parallel<br />
camera support for 8- and 10-bit<br />
ITU656 video, up to 24-bit digital<br />
RGB<br />
• Three synchronous audio<br />
interfaces implementing fullduplex<br />
serial interfaces with frame<br />
synchronization such as I2S, AC97,<br />
and CODEC/DSP interfaces<br />
• Optional enhanced serial audio<br />
interface which provides a fullduplex<br />
serial port for communication<br />
with a variety of serial devices,<br />
including industry-standard codecs,<br />
SPDIF transceivers and other<br />
processors<br />
• Asynchronous sample rate converter<br />
for rate conversion between 32,<br />
44.1, 48 and 96 kHz<br />
Connectivity and<br />
Communications<br />
• USB 2.0 OTG controller with<br />
integrated PHY<br />
• 10/100 Ethernet controllers<br />
• Layer 2 Ethernet switch<br />
• Four UARTs with IrDA support<br />
including two UART with ISO7816<br />
smart card support. Variety of data<br />
size, format and transmission/<br />
reception settings supported for<br />
multiple industrial communication<br />
protocols<br />
• Two CAN modules for industrial<br />
network bridging<br />
• Three DSPI and two I2C interfaces<br />
freescale.com/Vybrid<br />
Reliability, Safety and<br />
Security<br />
• TrustZone Address Space Controllers<br />
provide memory protection for all<br />
masters on the crossbar switch,<br />
increasing software reliability<br />
• Cyclic redundancy check engine<br />
validates memory contents and<br />
communication data, increasing<br />
system reliability<br />
• Independent-clocked COP guards<br />
against clock skew or code runaway<br />
for fail-safe applications such as<br />
the IEC 60730 safety standard for<br />
household appliances<br />
• External watchdog monitor drives<br />
output pin to safe state external<br />
components if watchdog event<br />
occurs<br />
Optional Secure<br />
Application Support<br />
• Cryptography acceleration and<br />
assurance module<br />
Supports acceleration and<br />
off-loading for selected crypto<br />
algorithms such as AES, DES, 3<br />
DES, ArcFour Symmetric key blog<br />
ciphers<br />
• Random number generation<br />
NIST compliant SP800-90<br />
Combination of a true random<br />
number generator and a pseudorandom<br />
number generator<br />
• Real-time integrity checker<br />
Periodic check on system<br />
memory for unauthorized<br />
modifications<br />
• Secure non-volatile storage<br />
Secure non-rollover real-time<br />
counter<br />
Non-rollover monotonic counter<br />
Zeroizable 256-bit secret key<br />
• Tamper detection<br />
Support for up to six external<br />
tamper detection inputs<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
External Peripheral Support<br />
• Secure digital host controller<br />
supports SD, SDIO, MMC or<br />
CE-ATA cards for in-application<br />
software upgrades, media files or<br />
adding Wi-Fi ® support<br />
• NAND flash controller supports up<br />
to 32-bit ECC current and future<br />
NAND types. ECC management<br />
handled in hardware, minimizing<br />
software overhead<br />
• FlexBus external bus interface<br />
provides glueless interface options<br />
to memories and peripherals such<br />
as graphics displays. Supports up<br />
to four chip selects<br />
Tools and Software<br />
• <strong>Freescale</strong> Tower System hardware<br />
development environment<br />
• Integrated development<br />
environments<br />
Reference MQX BSP<br />
CodeWarrior V10.x (Eclipse) IDE<br />
with Processor Expert software<br />
ARM DS5 MDK<br />
Runtime software<br />
Math and encryption libraries<br />
Motor control libraries<br />
Lightweight media framework<br />
Complimentary bootloaders<br />
(USB, Ethernet, RF, serial)<br />
Complimentary <strong>Freescale</strong><br />
embedded GUI software driver<br />
for graphics LCD panels<br />
Complimentary <strong>Freescale</strong> MQX<br />
Cost-effective Nano SSL/<br />
Nano SSH for <strong>Freescale</strong><br />
MQX RTOS<br />
• Full ARM ecosystem<br />
9
Vybrid Family Back to Table of Contents<br />
Vybrid VF4xx Family<br />
Single core solution with dual USB and integrated PHY<br />
for mobility and automation<br />
The VF4xx family features<br />
the ARM ® Cortex-A5 core<br />
with speeds up to 500 MHz<br />
with 512 KB L2 cache, dual<br />
USB 2.0 OTG controllers<br />
with integrated PHY, 1 MB<br />
of on-chip SRAM and a rich<br />
suite of communication,<br />
connectivity and humanmachine<br />
interfaces (HMI).<br />
Target Applications<br />
• Building automation<br />
• Gaming controllers<br />
• Point-of-sale<br />
Mixed-Signal Capability<br />
• Two 12-bit ADCs with configurable<br />
resolution. Single or differential<br />
output mode operation for<br />
improved noise rejection. 500<br />
ns conversion time achievable<br />
with programmable delay block<br />
triggering<br />
• Two 12-bit DACs for analog<br />
waveform generation for audio<br />
applications or sensor manipulation<br />
Memory<br />
• Dual Quad SPI supporting a double<br />
data rate interface, an enhanced<br />
read data buffering scheme,<br />
Execute-in-Place and support for<br />
dual-die flashes<br />
• Boot ROM with optional high<br />
assurance boot for secure booting<br />
capability<br />
• Up to 1 MB on-chip SRAM with<br />
ECC support on 512 KB<br />
10<br />
Vybrid VF4xx Family<br />
Faraday F400 Block Diagram<br />
Debug and Trace<br />
JTAG<br />
Trace<br />
Timers<br />
FlexTimer (8-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (8-ch.)<br />
IEEE ® 1588 Timers<br />
Periodic Interrupt Timers<br />
Low Power Timers<br />
Memory<br />
Boot ROM<br />
1 MB SRAM<br />
Memory Interfaces<br />
DDR Controller<br />
NAND Flash Controller<br />
Quad SPI x2<br />
External Bus Interface<br />
• 16-bit DDR controller with PHY<br />
and ECC support capable of<br />
DDR3/LPDDR2 800 MHz data rate<br />
Performance<br />
System<br />
AMBA NIC<br />
Internal and<br />
External Watchdog<br />
Interrupt<br />
Router<br />
DMA<br />
Up to 64-ch.<br />
Power Management<br />
Regulators<br />
Memory Protection<br />
Unit<br />
TFT LCD<br />
Touch Screen Controller<br />
Video<br />
Video Interface w/Camera<br />
Audio<br />
• ARM Cortex-A5 core with<br />
frequency up to 500 MHz, with<br />
double precision floating point,<br />
NEON media processing engine<br />
for acceleration of media and<br />
signal processing, and TrustZone<br />
security extension. 32 KB each of<br />
instruction and data L1 cache and<br />
512 KB L2 cache for optimized<br />
bus bandwidth and on-chip SRAM<br />
execution performance<br />
• Up to 64-channel DMA for<br />
peripheral and memory servicing<br />
with reduced CPU loading and<br />
faster system throughput<br />
ARM ® Cortex-A5<br />
Up to 500 MHz<br />
• Crossbar switch enables<br />
concurrent multi-master bus<br />
accesses, increasing bus<br />
bandwidth<br />
Timing and Control<br />
• Four flex timers with a total of 20<br />
channels. Hardware dead-time<br />
insertion and quadrature decoding<br />
for motor control<br />
• Four-channel 32-bit periodic<br />
interrupt timer provides time base<br />
for RTOS task scheduler or trigger<br />
source for ADC conversion and<br />
programmable delay block<br />
HMI<br />
Core<br />
DP-FPU<br />
NEON<br />
L1 I/D-Cache<br />
L2 Cache<br />
Trace/Debug<br />
GIC<br />
Display Security<br />
ASRC<br />
SAI x4<br />
ESAI<br />
Crypytography Module<br />
Tamper Detect<br />
Secure RTC<br />
Secure RTIC<br />
Secure RAM<br />
Secure Fuses<br />
Secure WDOG<br />
Secure JTAG<br />
Analog<br />
12-bit ADC x2<br />
12-bit DAC x2<br />
PLL<br />
Clocks<br />
Clock<br />
Monitors<br />
Internal Reference<br />
Clocks<br />
Low/High Frequency<br />
Oscillators<br />
Communication<br />
UART x6 CAN x2<br />
DSPI x4 I 2 C x4<br />
IEEE 1588<br />
Ethernet<br />
USB Host + PHY<br />
LS/FS/HS<br />
USB OTG + PHY<br />
LS/FS/HS<br />
Secure Digital x2<br />
141 GPIO<br />
(with Interrupt)<br />
• TFT LCD display capable of up to<br />
XGA resolution
Back to Table of Contents<br />
• Four-wire touch screen controller<br />
for resistive touch screens<br />
• Xtrinsic low-power touch-sensing<br />
interface with up to 16 inputs.<br />
Operates in all low-power modes.<br />
Hardware implementation avoids<br />
software polling method. High<br />
sensitivity level allows use of<br />
overlay surfaces up to 5 mm thick<br />
Multimedia<br />
• Video interface unit with parallel<br />
camera support for 8- and 10-bit<br />
ITU656 video, up to 24-bit digital<br />
RGB<br />
• Up to four synchronous audio<br />
interfaces implementing fullduplex<br />
serial interfaces with frame<br />
synchronization such as I 2 S, AC97,<br />
and CODEC/DSP interfaces<br />
• Enhanced serial audio interface<br />
which provides a full-duplex serial<br />
port for serial communication with<br />
a variety of serial devices, including<br />
industry-standard codecs, SPDIF<br />
transceivers and other processors<br />
• Asynchronous sample rate<br />
converter for rate conversion<br />
between 32, 44.1, 48 and 96 kHz<br />
Connectivity and<br />
Communications<br />
• Dual USB 2.0 OTG controller with<br />
integrated PHY<br />
• 10/100 Ethernet controller<br />
• Up to six UARTs, with IrDA support<br />
including two UARTs with ISO7816<br />
smart card support. Variety of data<br />
size, format and transmission/<br />
reception settings supported for<br />
multiple industrial communication<br />
protocols<br />
• Two CAN modules for industrial<br />
network bridging<br />
• Four DSPI and four I 2 C interfaces<br />
freescale.com/Vybrid<br />
Reliability, Safety and<br />
Security<br />
• TrustZone Address Space<br />
Controllers provide memory<br />
protection for all masters on<br />
the crossbar switch, increasing<br />
software reliability<br />
• Cyclic redundancy check engine<br />
validates memory contents and<br />
communication data, increasing<br />
system reliability<br />
• Independent-clocked COP guards<br />
against clock skew or code<br />
runaway for fail-safe applications<br />
such as IEC 60730 safety standard<br />
for household appliances<br />
• External watchdog monitor drives<br />
output pin to safe state external<br />
components if watchdog event<br />
occurs<br />
Optional Secure<br />
Application Support<br />
• Cryptography acceleration and<br />
assurance module<br />
Supports acceleration and<br />
off-loading for selected crypto<br />
algorithms such as AES, DES,<br />
3 DES, ArcFour Symmetric key<br />
blog ciphers<br />
• Random number generation<br />
NIST compliant SP800-90<br />
Combination of a true random<br />
number generator and a pseudorandom<br />
number generator<br />
• Real-time integrity checker<br />
Periodic check on system<br />
memory for unauthorized<br />
modifications<br />
• Secure non-volatile storage<br />
Secure non-rollover real-time<br />
counter<br />
Non-rollover monotonic counter<br />
Zeroizable 256-bit secret key<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Tamper detection<br />
Support for up to 10 external<br />
passive tamper detection pins<br />
or five active external tamper<br />
detection pin pairs<br />
External Peripheral Support<br />
• Secure digital host controller<br />
supports SD, SDIO, MMC or<br />
CE-ATA cards for in-application<br />
software upgrades, media files or<br />
adding Wi-Fi ® support<br />
• NAND flash controller supports up<br />
to 32-bit ECC current and future<br />
NAND types. ECC management<br />
handled in hardware, minimizing<br />
software overhead<br />
• FlexBus external bus interface<br />
provides glueless interface options<br />
to memories and peripherals such<br />
as graphics displays. Supports up<br />
to four chip selects<br />
Tools and Software<br />
• <strong>Freescale</strong> Tower System hardware<br />
development environment<br />
• Integrated development<br />
environments<br />
Reference Linux BSP<br />
Reference MQX BSP<br />
CodeWarrior V10.x (Eclipse) IDE<br />
with Processor Expert software<br />
ARM DS5 MDK<br />
Runtime software<br />
Math and encryption libraries<br />
Media framework<br />
Complimentary bootloaders<br />
(USB, Ethernet, RF, serial)<br />
Complimentary <strong>Freescale</strong><br />
embedded GUI software driver<br />
for graphics LCD panels<br />
Complimentary <strong>Freescale</strong> MQX<br />
Cost-effective Nano SSL/<br />
Nano SSH for <strong>Freescale</strong> MQX<br />
RTOS<br />
• Full ARM ecosystem<br />
11
Vybrid Family<br />
Back to Table of Contents<br />
Vybrid VF5xx Family<br />
Single core solution with dual Ethernet and L2 switch<br />
for automation and control<br />
The VF5xx family features<br />
the ARM ® Cortex-A5 core<br />
with speeds up to 500 MHz<br />
with 512 KB L2 cache, dual<br />
USB 2.0 OTG controllers<br />
with integrated PHY, dual<br />
10/100 Ethernet controllers<br />
with L2 switch, 1 MB of<br />
on-chip SRAM and a rich<br />
suite of communication,<br />
connectivity and humanmachine<br />
interfaces (HMI).<br />
The VF5xx family is pin and<br />
software compatible with<br />
the VF4xx family.<br />
Target Applications<br />
• Industrial control<br />
• Networked HVAC systems<br />
• Portable consumer devices<br />
• Networked audio system<br />
Mixed-Signal Capability<br />
• Two 12-bit ADCs with configurable<br />
resolution. Single or differential<br />
output mode operation for improved<br />
noise rejection. 500 ns conversion<br />
time achievable with programmable<br />
delay block triggering<br />
• Two 12-bit DACs for analog<br />
waveform generation for audio<br />
applications or sensor manipulation<br />
Memory<br />
• Dual Quad SPI supporting a double<br />
data rate interface, an enhanced<br />
read data buffering scheme,<br />
Execute-in-Place and support for<br />
dual-die flashes<br />
12<br />
Vybrid VF5xx Family<br />
Faraday F500 Block Diagram<br />
Debug and Trace<br />
JTAG<br />
Trace<br />
Timers<br />
FlexTimer (8-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (8-ch.)<br />
IEEE ® 1588 Timers<br />
Periodic Interrupt Timers<br />
Low Power Timers<br />
Memory<br />
Boot ROM<br />
1 MB SRAM<br />
Memory Interfaces<br />
DDR Controller<br />
NAND Flash Controller<br />
Quad SPI x2<br />
External Bus Interface<br />
• Boot ROM with optional high<br />
assurance boot for secure booting<br />
capability<br />
• Up to 1 MB on-chip SRAM with<br />
ECC support on 512 KB<br />
• 16-bit DDR controller with PHY and<br />
ECC support capable of DDR3/<br />
LPDDR2 800 MHz data rate<br />
Performance<br />
System<br />
AMBA NIC<br />
Internal and<br />
External Watchdog<br />
Interrupt<br />
Router<br />
DMA<br />
Up to 64-ch.<br />
Power Management<br />
Regulators<br />
Memory Protection<br />
Unit<br />
• ARM Cortex-A5 core with<br />
frequency up to 500 MHz, with<br />
double precision floating point,<br />
NEON media processing engine<br />
for acceleration of media and<br />
signal processing, and TrustZone<br />
security extension. 32 KB each of<br />
instruction and data L1 cache and<br />
512 KB L2 cache for optimized<br />
bus bandwidth and on-chip SRAM<br />
execution performance<br />
Core<br />
ARM ® Cortex-A5<br />
Up to 500 MHz<br />
DP-FPU<br />
NEON<br />
L1 I/D-Cache<br />
L2 Cache<br />
Trace/Debug<br />
GIC<br />
Display Security<br />
TFT LCD<br />
Crypytography Module<br />
Touch Screen Controller<br />
Tamper Detect<br />
Video<br />
Secure RTC<br />
Video Interface w/Camera<br />
OpenVG GPU<br />
Secure RTIC<br />
Audio<br />
Secure RAM<br />
ASRC<br />
Secure Fuses<br />
SAI x4<br />
ESAI<br />
Secure WDOG<br />
SPDIF<br />
Secure JTAG<br />
• Up to 64-channel DMA for<br />
peripheral and memory servicing<br />
with reduced CPU loading and<br />
faster system throughput<br />
• Crossbar switch enables concurrent<br />
multi-master bus accesses,<br />
increasing bus bandwidth<br />
Timing and Control<br />
Analog<br />
12-bit ADC x2<br />
12-bit DAC x2<br />
PLL<br />
Clocks<br />
Clock<br />
Monitors<br />
Internal Reference<br />
Clocks<br />
Low/High Frequency<br />
Oscillators<br />
Communication<br />
UART x6 CAN x2<br />
DSPI x4 I<br />
IEEE 1588<br />
Ethernet x2<br />
L2Switch<br />
USB Host + PHY<br />
LS/FS/HS<br />
USB OTG + PHY<br />
LS/FS/HS<br />
Secure Digital x2<br />
141 GPIO<br />
(with Interrupt)<br />
2C x4<br />
• Four flex timers with a total of 20<br />
channels. Hardware dead-time<br />
insertion and quadrature decoding<br />
for motor control<br />
• Four-channel 32-bit periodic<br />
interrupt timer provides time base<br />
for RTOS task scheduler or trigger<br />
source for ADC conversion and<br />
programmable delay block
HMI<br />
Back to Table of Contents<br />
• TFT LCD display capable of XGA<br />
resolution<br />
• Four-wire touch screen controller for<br />
resistive touch screens<br />
• Xtrinsic low-power touch-sensing<br />
interface with up to 16 inputs.<br />
Operates in all low-power modes.<br />
Hardware implementation avoids<br />
software polling method<br />
• High sensitivity level allows use of<br />
overlay surfaces up to 5 mm thick<br />
Multimedia<br />
• Video interface unit with parallel<br />
camera support for 8- and 10-bit<br />
ITU656 video, up to 24-bit digital RGB<br />
• OpenVG GPU for UI acceleration<br />
• Up to four synchronous audio<br />
interfaces implementing fullduplex<br />
serial interfaces with frame<br />
synchronization such as I2S, AC97,<br />
and CODEC/DSP interfaces<br />
• Optional enhanced serial audio<br />
interface which provides a fullduplex<br />
serial port for serial<br />
communication with a variety<br />
of serial devices, including<br />
industry-standard codecs, SPDIF<br />
transceivers, and other processors<br />
• Sony Philips Digital Interface<br />
receives and transmits digital audio<br />
using the IEC60958 standard<br />
consumer format<br />
• Asynchronous sample rate<br />
converter for rate conversion<br />
between 32, 44.1, 48 and 96 kHz<br />
Connectivity and<br />
Communications<br />
• Dual USB 2.0 OTG controller with<br />
integrated PHY<br />
• Dual 10/100 Ethernet controller<br />
• Layer 2 Ethernet switch<br />
• Up to six UARTs, with IrDA support<br />
including two UARTs with ISO7816<br />
smart card support. Variety of data<br />
size, format and transmission/<br />
reception settings supported for<br />
freescale.com/Vybrid<br />
multiple industrial communication<br />
protocols<br />
• Two CAN modules for industrial<br />
network bridging<br />
• Four DSPI and four I2C interfaces<br />
Reliability, Safety and<br />
Security<br />
• TrustZone Address Space Controllers<br />
provide memory protection for all<br />
masters on the crossbar switch,<br />
increasing software reliability<br />
• Cyclic redundancy check engine<br />
validates memory contents and<br />
communication data, increasing<br />
system reliability<br />
• Independent-clocked COP guards<br />
against clock skew or code runaway<br />
for fail-safe applications such as<br />
the IEC 60730 safety standard for<br />
household appliances<br />
• External watchdog monitor drives<br />
output pin to safe state external<br />
components if watchdog event occurs<br />
Optional Secure<br />
Application Support<br />
• Cryptography acceleration and<br />
assurance module<br />
Supports acceleration and<br />
off-loading for selected crypto<br />
algorithms such as AES, DES, 3<br />
DES, ArcFour Symmetric key blog<br />
ciphers<br />
• Random number generation<br />
NIST compliant SP800-90<br />
Combination of a true random<br />
number generator and a pseudorandom<br />
number generator<br />
• Real time integrity checker<br />
Periodic check on system<br />
memory for unauthorized<br />
modifications<br />
• Secure non-volatile storage<br />
Secure non-rollover real-time<br />
counter<br />
Non-rollover monotonic counter<br />
Zeroizable 256-bit secret key<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Tamper detection<br />
Support for up to 10 external<br />
passive tamper detection pins<br />
or five active external tamper<br />
detection pin pairs<br />
External Peripheral Support<br />
• Secure digital host controller<br />
supports SD, SDIO, MMC or<br />
CE-ATA cards for in-application<br />
software upgrades, media files or<br />
adding Wi-Fi ® support<br />
• NAND flash controller supports up<br />
to 32-bit ECC current and future<br />
NAND types. ECC management<br />
handled in hardware, minimizing<br />
software overhead<br />
• FlexBus external bus interface<br />
provides glueless interface options<br />
to memories and peripherals such<br />
as graphics displays. Supports up<br />
to four chip selects<br />
Tools and Software<br />
• <strong>Freescale</strong> Tower System hardware<br />
development environment<br />
• Integrated development<br />
environments<br />
Reference Linux BSP<br />
Reference MQX BSP<br />
CodeWarrior V10.x (Eclipse) IDE<br />
with Processor Expert software<br />
ARM DS5 MDK<br />
Runtime software<br />
Math and encryption libraries<br />
Media framework<br />
Complimentary bootloaders (USB,<br />
Ethernet, RF, serial)<br />
Complimentary <strong>Freescale</strong><br />
embedded GUI (eGUI) software<br />
driver for graphics LCD panels<br />
Complimentary <strong>Freescale</strong> MQX<br />
Cost-effective Nano SSL/<br />
Nano SSH for <strong>Freescale</strong> MQX<br />
RTOS<br />
• Full ARM ecosystem<br />
13
Vybrid Family<br />
Back to Table of Contents<br />
Vybrid VF6xx Family<br />
Dual heterogeneous core solution with XGA display, dual USB,<br />
dual Ethernet and L2 switch for automation and HMI<br />
The VF6xx is the<br />
heterogeneous dualcore<br />
family combining the<br />
ARM ® Cortex-A5 and<br />
Cortex-M4 cores.<br />
It includes dual USB 2.0 OTG<br />
controllers with integrated<br />
PHY, dual 10/100 Ethernet<br />
controllers with L2 switch,<br />
1 MB of on-chip SRAM and a<br />
rich suite of communication,<br />
connectivity and humanmachine<br />
interfaces (HMI).<br />
Target Applications<br />
• Industrial automation<br />
• Health care systems<br />
• Multi-lane point-of-sale<br />
• Buildling control<br />
Mixed-Signal Capability<br />
• Two 12-bit ADCs with configurable<br />
resolution. Single or differential<br />
output mode operation for improved<br />
noise rejection. 500 ns conversion<br />
time achievable with programmable<br />
delay block triggering<br />
• Two 12-bit DACs for analog<br />
waveform generation for audio<br />
applications or sensor manipulation<br />
Memory<br />
• Dual Quad SPI supporting a double<br />
data rate interface, an enhanced read<br />
data buffering scheme, Executein-Place<br />
and support for dual-die<br />
flashes<br />
• Boot ROM with optional high<br />
assurance boot for secure booting<br />
capability<br />
14<br />
Vybrid VF6xx Family<br />
Vybrid V600 Block Diagram<br />
Debug and Trace<br />
JTAG<br />
Trace<br />
Timers<br />
FlexTimer (8-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (8-ch.)<br />
IEEE ® 1588 Timers<br />
Periodic Interrupt Timers<br />
Low Power Timers<br />
Memory<br />
Boot ROM<br />
1 MB SRAM<br />
Memory Interfaces<br />
DDR Controller<br />
NAND Flash Controller<br />
Quad SPI x2<br />
External Bus Interface<br />
• Up to 1 MB on-chip SRAM with<br />
ECC support on 512 KB<br />
• 16-bit DDR controller with PHY and<br />
ECC support capable of DDR3/<br />
LPDDR2 800 MHz data rate<br />
Performance<br />
Core<br />
ARM ® Cortex-A5<br />
Up to 500 MHz<br />
DP-FPU<br />
NEON<br />
L1 I/D-Cache<br />
L2 Cache<br />
Trace/Debug<br />
GIC<br />
• ARM Cortex-A5 core with frequency<br />
up to 500 MHz, with 32 KB each<br />
instruction and data L1 cache<br />
and 512 KB L2 cache double<br />
precision floating point, NEON media<br />
processing engine for acceleration<br />
of media and signal processing, and<br />
TrustZone security extension<br />
• ARM Cortex-M4 core running<br />
up to 167 MHz, with 16 KB of<br />
instruction/data L1 cache plus 64<br />
KB of tightly coupled memory,<br />
DSP support for single cycle<br />
32-bit MAC, single instruction<br />
System<br />
AMBA NIC<br />
Internal and<br />
External Watchdog<br />
Interrupt<br />
Router<br />
DMA<br />
Up to 64-ch.<br />
Power<br />
Management<br />
Regulators<br />
Memory<br />
Protection<br />
Unit<br />
Core<br />
ARM ® Cortex-M4<br />
Up to 167 MHz<br />
SP-FPU<br />
DSP<br />
Trace/Debug<br />
I/D-Cache<br />
NVIC<br />
Display Security<br />
TFT LCD<br />
Crypytography Module<br />
Touch Screen Controller<br />
Tamper Detect<br />
Video<br />
Video Interface w/Camera<br />
Secure RTC<br />
OpenVG GPU<br />
Secure RTIC<br />
Audio<br />
Secure RAM<br />
ASRC<br />
Secure Fuses<br />
SAI x4<br />
ESAI<br />
Secure WDOG<br />
SPDIF<br />
Secure JTAG<br />
multiple data extensions and single<br />
precision floating point unit<br />
• Up to 64-channel DMA for<br />
peripheral and memory servicing<br />
with reduced CPU loading and<br />
faster system throughput<br />
• Crossbar switch enables concurrent<br />
multi-master bus accesses,<br />
increasing bus bandwidth<br />
Timing and Control<br />
Analog<br />
12-bit ADC x2<br />
12-bit DAC x2<br />
PLL<br />
Clocks<br />
Clock<br />
Monitors<br />
Internal Reference<br />
Clocks<br />
Low/High Frequency<br />
Oscillators<br />
Communication<br />
UART x6 CAN x2<br />
DSPI x4 I<br />
IEEE 1588<br />
Ethernet x2<br />
L2Switch<br />
USB Host + PHY<br />
LS/FS/HS<br />
USB OTG + PHY<br />
LS/FS/HS<br />
Secure Digital x2<br />
141 GPIO<br />
(with Interrupt)<br />
2C x4<br />
• Four flex timers with a total of 20<br />
channels. Hardware dead-time<br />
insertion and quadrature decoding<br />
for motor control<br />
• Four-channel 32-bit periodic<br />
interrupt timer provides time base<br />
for RTOS task scheduler or trigger<br />
source for ADC conversion and<br />
programmable delay block
HMI<br />
Back to Table of Contents<br />
• TFT LCD display capable of up to<br />
XGA resolution<br />
• Four-wire touch screen controller for<br />
resistive touch screens<br />
• Xtrinsic low power touch-sensing<br />
interface with up to 16 inputs.<br />
Operates in all low-power modes<br />
(minimum current adder when<br />
enabled). Hardware implementation<br />
avoids software polling method.<br />
High sensitivity level allows use of<br />
overlay surfaces up to 5 mm thick<br />
Multimedia<br />
• Video interface unit with parallel<br />
camera support for 8- and 10-bit<br />
ITU656 video, up to 24-bit digital<br />
RGB<br />
• OpenVG GPU for UI acceleration<br />
• Up to four synchronous audio<br />
interfaces implementing fullduplex<br />
serial interfaces with frame<br />
synchronization such as I2S, AC97,<br />
and CODEC/DSP interfaces<br />
• Optional enhanced serial audio<br />
interface which provides a fullduplex<br />
serial port for serial<br />
communication with a variety<br />
of serial devices, including<br />
industry-standard codecs, SPDIF<br />
transceivers and other processors<br />
• Sony Philips Digital Interface<br />
receives and transmits digital audio<br />
using the IEC60958 standard<br />
consumer format<br />
• Asynchronous Sample Rate<br />
Converter for rate conversion<br />
between 32, 44.1, 48 and 96 kHz<br />
Connectivity and<br />
Communications<br />
• Dual USB 2.0 OTG controller with<br />
integrated PHY<br />
• Dual 10/100 Ethernet controller<br />
• Layer 2 Ethernet switch<br />
• Up to six UARTs, with IrDA support<br />
including two UARTs with ISO7816<br />
smart card support. Variety of data<br />
size, format and transmission/reception<br />
freescale.com/Vybrid<br />
settings supported for multiple<br />
industrial communication protocols<br />
• Two CAN modules for industrial<br />
network bridging<br />
• Four DSPI and four I2C interfaces<br />
Reliability, Safety and<br />
Security<br />
• TrustZone Address Space Controllers<br />
provide memory protection for all<br />
masters on the crossbar switch,<br />
increasing software reliability<br />
• Cyclic redundancy check engine<br />
validates memory contents and<br />
communication data, increasing<br />
system reliability<br />
• Independent-clocked COP guards<br />
against clock skew or code runaway<br />
for fail-safe applications such as<br />
the IEC 60730 safety standard for<br />
household appliances<br />
• External watchdog monitor drives<br />
output pin to safe state external<br />
components if watchdog event occurs<br />
Optional Secure<br />
Application Support<br />
• Cryptography acceleration and<br />
assurance module<br />
Supports acceleration and<br />
off-loading for selected crypto<br />
algorithms such as AES, DES, 3<br />
DES, ArcFour Symmetric key<br />
blog ciphers<br />
• Random number generation<br />
NIST compliant SP800-90<br />
Combination of a true random<br />
number generator and a pseudorandom<br />
number generator<br />
• Real-time integrity checker<br />
Periodic check on system<br />
memory for unauthorized<br />
modifications<br />
• Secure non-volatile storage<br />
Secure non-rollover real-time<br />
counter<br />
Non-rollover monotonic counter<br />
Zeroizable 256-bit secret key<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Tamper detection<br />
Support for up to 10 external<br />
passive tamper detection pins<br />
or five active external tamper<br />
detection pin pairs<br />
External Peripheral Support<br />
• Secure digital host controller<br />
supports SD, SDIO, MMC or<br />
CE-ATA cards for in-application<br />
software upgrades, media files or<br />
adding Wi-Fi ® support<br />
• NAND flash controller supports up<br />
to 32-bit ECC current and future<br />
NAND types. ECC management<br />
handled in hardware, minimizing<br />
software overhead<br />
• FlexBus external bus interface<br />
provides glueless interface options<br />
to memories and peripherals such<br />
as graphics displays. Supports up<br />
to four chip selects<br />
Tools and Software<br />
• <strong>Freescale</strong> Tower System hardware<br />
development environment<br />
• Integrated development<br />
environments<br />
Reference Linux BSP<br />
Reference MQX BSP<br />
CodeWarrior V10.x (Eclipse) IDE<br />
with Processor Expert software<br />
ARM DS5 MDK<br />
IAR Embedded Workbench<br />
Runtime software and RTOS<br />
Math and encryption libraries<br />
Media framework<br />
Motor control libraries<br />
Complimentary bootloaders (USB,<br />
Ethernet, RF, serial)<br />
Complimentary <strong>Freescale</strong><br />
embedded GUI (eGUI) software<br />
driver for graphics LCD panels<br />
Complimentary <strong>Freescale</strong> MQX<br />
Cost-effective Nano SSL/Nano<br />
SSH for <strong>Freescale</strong> MQX RTOS<br />
• Full ARM ecosystem<br />
15
Vybrid Family Back to Table of Contents<br />
Vybrid VF7xx Family<br />
Dual heterogeneous core solution with dual XGA display,<br />
GPU for portable systems<br />
The VF7xx dual<br />
heterogeneous core<br />
solution combines the<br />
ARM ® Cortex-A5 and<br />
Cortex-M4 cores. Features<br />
include dual TFT LCD<br />
support up to XGA resolution,<br />
dual USB 2.0 OTG controllers<br />
with integrated PHY, 10/100<br />
Ethernet controller, 1 MB of<br />
on-chip SRAM and a rich<br />
suite of communication,<br />
connectivity and humanmachine<br />
interfaces (HMI).<br />
Target Applications<br />
• Cost-sensitive gaming systems<br />
• Portable data terminals<br />
• Internet appliances<br />
• Mid-range white goods/appliances<br />
Mixed-Signal Capability<br />
• Two 12-bit ADCs with configurable<br />
resolution. Single or differential<br />
output mode operation for improved<br />
noise rejection. 500 ns conversion<br />
time achievable with programmable<br />
delay block triggering<br />
• Two 12-bit DACs for analog<br />
waveform generation for audio<br />
applications or sensor manipulation<br />
Memory<br />
• Dual Quad SPI supporting a double<br />
data rate interface, an enhanced read<br />
data buffering scheme, Execute-in-<br />
Place and support for dual-die flashes<br />
• Boot ROM with optional high<br />
assurance boot for secure booting<br />
capability<br />
16<br />
Vybrid VF7xx Family<br />
Vybrid V700 Block Diagram<br />
Debug and Trace<br />
JTAG<br />
Trace<br />
Timers<br />
FlexTimer (8-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (2-ch.)<br />
FlexTimer (8-ch.)<br />
IEEE ® 1588 Timers<br />
Periodic Interrupt Timers<br />
Low Power Timers<br />
Memory<br />
Boot ROM<br />
1 MB SRAM<br />
Memory Interfaces<br />
DDR Controller<br />
NAND Flash Controller<br />
Quad SPI x2<br />
External Bus Interface<br />
• Up to 1 MB SRAM with ECC on<br />
512 KB<br />
• 16-bit DDR controller with PHY and<br />
ECC support capable of DDR3/<br />
LPDDR2 800 MHz data rate<br />
Performance<br />
Core<br />
ARM ® Cortex-A5<br />
Up to 500 MHz<br />
DP-FPU<br />
NEON<br />
L1 I/D-Cache<br />
L2 Cache<br />
Trace/Debug<br />
GIC<br />
• ARM Cortex-A5 core with frequency<br />
up to 500 MHz, with 32 KB each<br />
instruction and data L1 cache<br />
and 512 KB L2 cache double<br />
precision floating point, NEON media<br />
processing engine for acceleration<br />
of media and signal processing, and<br />
TrustZone security extension<br />
• ARM Cortex-M4 core running up to<br />
167 MHz, with 16 KB of instruction/<br />
data L1 cache plus 64 KB of tightly<br />
coupled memory, DSP support<br />
for single cycle 32-bit MAC, single<br />
instruction multiple data extensions<br />
and single precision floating point unit<br />
System<br />
AMBA NIC<br />
Internal and<br />
External Watchdog<br />
Interrupt<br />
Router<br />
DMA<br />
Up to 64-ch.<br />
Power<br />
Management<br />
Regulators<br />
Memory<br />
Protection<br />
Unit<br />
• Up to 64-channel DMA for<br />
peripheral and memory servicing<br />
with reduced CPU loading and<br />
faster system throughput<br />
• Crossbar switch enables concurrent<br />
multi-master bus accesses,<br />
increasing bus bandwidth<br />
Timing and Control<br />
• Four flex timers with a total of 20<br />
channels. Hardware dead-time<br />
insertion and quadrature decoding<br />
for motor control<br />
• Four-channel 32-bit periodic<br />
interrupt timer provides time base<br />
for RTOS task scheduler or trigger<br />
source for ADC conversion and<br />
programmable delay block<br />
HMI<br />
Core<br />
ARM ® Cortex-M4<br />
Up to 167 MHz<br />
SP-FPU<br />
DSP<br />
Trace/Debug<br />
I/D-Cache<br />
NVIC<br />
Display Security<br />
TFT LCD<br />
Touch Screen Controller<br />
Video<br />
Crypytography Module<br />
Tamper Detect<br />
Video Interface w/Camera<br />
Secure RTC<br />
Video ADC<br />
OpenVG GPU<br />
Secure RTIC<br />
Secure RAM<br />
Audio<br />
ASRC<br />
Secure Fuses<br />
SAI x4<br />
ESAI<br />
Secure WDOG<br />
SPDIF<br />
Secure JTAG<br />
Analog<br />
12-bit ADC x2<br />
12-bit DAC x2<br />
PLL<br />
Clocks<br />
Clock<br />
Monitors<br />
Internal Reference<br />
Clocks<br />
Low/High Frequency<br />
Oscillators<br />
Communication<br />
UART x6 CAN x2<br />
DSPI x4 I 2 C x4<br />
IEEE 1588<br />
Ethernet<br />
USB Host + PHY<br />
LS/FS/HS<br />
USB OTG + PHY<br />
LS/FS/HS<br />
Secure Digital x2<br />
141 GPIO<br />
(with Interrupt)<br />
• Dual TFT LCD display capable of up<br />
to XGA resolution
Back to Table of Contents<br />
• Four-wire touch screen controller for<br />
resistive touch screens<br />
• Xtrinsic low power touch-sensing<br />
interface with up to 16 inputs.<br />
Operates in all low-power modes<br />
(minimum current adder when<br />
enabled). Hardware implementation<br />
avoids software polling method.<br />
High sensitivity level allows use of<br />
overlay surfaces up to 5 mm thick<br />
Multimedia<br />
• Video interface unit with parallel<br />
camera support for 8- and 10-bit<br />
ITU656 video, up to 18-bit digital RGB<br />
• OpenVG GPU for UI acceleration<br />
• Up to four synchronous audio<br />
interfaces implementing fullduplex<br />
serial interfaces with frame<br />
synchronization such as I2S, AC97,<br />
and CODEC/DSP interfaces<br />
• Optional enhanced serial audio<br />
interface which provides a fullduplex<br />
serial port for serial<br />
communication with a variety<br />
of serial devices, including<br />
industry-standard codecs, SPDIF<br />
transceivers, and other processors<br />
• Sony Philips Digital Interface<br />
receives and transmits digital audio<br />
using the IEC60958 standard<br />
consumer format<br />
• Asynchronous sample rate converter<br />
for rate conversion between 32,<br />
44.1, 48 and 96 kHz<br />
Connectivity and<br />
Communications<br />
• Dual USB 2.0 OTG controller with<br />
integrated PHY<br />
• 10/100 Ethernet controller<br />
• Up to six UARTs, with IrDA support<br />
including two UARTs with ISO7816<br />
smart card support. Variety of data<br />
size, format and transmission/<br />
reception settings supported for<br />
multiple industrial communication<br />
protocols<br />
• Two CAN modules for industrial<br />
network bridging<br />
• Four DSPI and four I2C interfaces<br />
freescale.com/Vybrid<br />
Reliability, Safety and<br />
Security<br />
• TrustZone Address Space Controllers<br />
provide memory protection for all<br />
masters on the cross bar switch,<br />
increasing software reliability<br />
• Cyclic redundancy check engine<br />
validates memory contents and<br />
communication data, increasing<br />
system reliability<br />
• Independent-clocked COP guards<br />
against clock skew or code runaway<br />
for fail-safe applications such as<br />
the IEC 60730 safety standard for<br />
household appliances<br />
• External watchdog monitor drives<br />
output pin to safe state external<br />
components if watchdog event occurs<br />
Optional Secure<br />
Application Support<br />
• Cryptography acceleration and<br />
assurance module<br />
Supports acceleration and<br />
off-loading for selected crypto<br />
algorithms like AES, DES, 3 DES,<br />
ArcFour Symmetric key blog<br />
ciphers<br />
• Random number generation<br />
NIST compliant SP800-90<br />
Combination of a true random<br />
number generator and a pseudorandom<br />
number generator<br />
• Real-time integrity checker<br />
Periodic check on system<br />
memory for unauthorized<br />
modifications<br />
• Secure non-volatile storage<br />
Secure non-rollover real-time<br />
counter<br />
Non-rollover monotonic counter<br />
Zeroizable 256-bit secret key<br />
• Tamper detection<br />
Support for up to 10 external<br />
passive tamper detection pins or<br />
up to five active external tamper<br />
detection pin pairs<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
External Peripheral Support<br />
• Secure digital host controller<br />
supports SD, SDIO, MMC or<br />
CE-ATA cards for in-application<br />
software upgrades, media files or<br />
adding Wi-Fi ® support<br />
• NAND flash controller supports up<br />
to 32-bit ECC current and future<br />
NAND types. ECC management<br />
handled in hardware, minimizing<br />
software overhead<br />
• FlexBus external bus interface<br />
provides glueless interface options<br />
to memories and peripherals such<br />
as graphics displays. Supports up<br />
to four chip selects<br />
Tools and Software<br />
• <strong>Freescale</strong> Tower System hardware<br />
development environment<br />
• Integrated development<br />
environments<br />
Reference Linux BSP<br />
Reference MQX BSP<br />
CodeWarrior V10.x (Eclipse) IDE<br />
with Processor Expert software<br />
ARM DS5 MDK<br />
IAR Embedded Workbench<br />
Runtime software and RTOS<br />
Math, DSP and encryption<br />
libraries<br />
Media framework<br />
Motor control libraries<br />
Complimentary bootloaders (USB,<br />
Ethernet, RF, serial)<br />
Complimentary <strong>Freescale</strong><br />
embedded GUI (eGUI) software<br />
driver for graphics LCD panels<br />
Complimentary <strong>Freescale</strong> MQX<br />
Cost-effective Nano SSL/<br />
Nano SSH for <strong>Freescale</strong> MQX<br />
RTOS<br />
• Full ARM ecosystem<br />
17
Technical Highlights
Core Technology<br />
ARM ® Cortex-A5 and ARM Cortex-M4 processors<br />
In developing a new generation, 40 nm<br />
integrated 32-bit family, <strong>Freescale</strong><br />
defined a dual-core architecture,<br />
combining the best features of the<br />
industry-standard ARM ® Cortex-A5<br />
application processor with the realtime<br />
focus of an ARM Cortex-M4<br />
control processor. Indeed, the 32-bit<br />
Vybrid family provides rich application<br />
capabilities with real-time control<br />
because each core has unique<br />
freescale.com/Vybrid<br />
attributes that make it the appropriate<br />
choice for specific embedded<br />
application spaces. The Vybrid family<br />
is ideally suited for automotive,<br />
industrial and general embedded<br />
applications. This solution is highly<br />
integrated, reducing system cost for<br />
the target applications. It includes<br />
a number of advanced architectural<br />
features so it can support either MCU<br />
or MPU configurations.<br />
Vybrid Processor Cores and Slave Memories Block Diagram<br />
Tag 7<br />
(Optional)<br />
Tag 0<br />
0<br />
1<br />
Data<br />
7<br />
RAM<br />
Array, 32K<br />
Tag/Data<br />
Arrays, 2x 8K<br />
The processor architecture can also<br />
be configured as a uniprocessor with<br />
either the ARM Cortex-A5 or the ARM<br />
Cortex-M4 as the operating core.<br />
For markets needing a single-core<br />
applications processor in the ARM<br />
Cortex family, the ARM Cortex-A5 is<br />
the best “value” application processor<br />
(in terms of MIPS/mW). Other key<br />
device components include a large<br />
ARM<br />
TPIU<br />
CTI<br />
DAP<br />
® Cortex-A5 Core Complex ARM ® Cortex Core Complex<br />
Debug (ITM, ETM, ETB, CTI)<br />
FPU + NEON<br />
NVIC FPU<br />
CM4 CPU<br />
FPB<br />
DWT<br />
Mul<br />
Inst<br />
ALU/Shift Q<br />
Ld/St<br />
PFU and Branch Predictor<br />
AP Bus Matrix ITM<br />
SystemBus CodeBus<br />
Data uTLB Inst uTLB<br />
TCMU<br />
TCML<br />
STB<br />
D-$<br />
TLB<br />
4 x 8K<br />
AXI BIU<br />
L2 Cache Controller<br />
AXI System Bus<br />
64<br />
DDRC Quad SPI<br />
I-$<br />
2 x 16K<br />
OCRAM<br />
_sys<br />
NIC-301<br />
OCRAM<br />
_sys<br />
OCRAM<br />
_gfx<br />
Boot<br />
ROM<br />
Sys-$<br />
AHB System Bus<br />
Sys<br />
BIU<br />
Code<br />
BIU<br />
FlexBus PBRIDGE<br />
Code-$<br />
Technical Highlights<br />
RAM<br />
Array, 32K<br />
Tag/Data<br />
Arrays, 2x 8K<br />
64 64<br />
64<br />
AHS Code Bus AHB Backdoor Port<br />
19
Technical Highlights<br />
on-chip RAM, display controller units,<br />
OpenVG graphics processing unit,<br />
Quad SPI interfaces to external flash<br />
memories and available RTOS. All<br />
these components combine to provide<br />
a low system cost BOM because<br />
DRAM is not required.<br />
Target applications for single-core ARM<br />
Cortex-M4/Cortex-A5 MPU devices in<br />
the multi-market, general embedded<br />
space include asset tracking devices,<br />
2D scanners, point-of-sale terminals,<br />
networked audio and data acquisition.<br />
In the industrial space, a single-core<br />
ARM Cortex-A5 MPU is targeted at<br />
industrial control, gas pumps and<br />
building control applications. Medical<br />
applications include patient monitoring<br />
and drug delivery mechanisms.<br />
A common theme in developing<br />
a dual-core architecture for these<br />
market segments is the inherent issues<br />
associated with a high-performance<br />
single (applications) processor running<br />
a high-level operating system coupled<br />
with the need for good real-time<br />
control. Vybrid devices address this<br />
growing number of consumer and<br />
industrial embedded applications that<br />
need higher application performance<br />
plus real-time responsiveness with its<br />
dual-core architecture combining the<br />
ARM Cortex-A5 application processor<br />
and the ARM Cortex-M4 for real-time<br />
control.<br />
This approach offers considerable<br />
flexibility in partitioning the software<br />
architecture across the dual-core<br />
hardware resources and provides<br />
options for reducing the RunIDD<br />
current consumption. It also removes<br />
the need for system designers to<br />
specify a higher performance single<br />
processor device in an effort to<br />
“oversample” the real-time events,<br />
thereby reducing system cost and<br />
power dissipation.<br />
20<br />
Vybrid Core Architecture Summary Comparison<br />
A “processor-centric” high-level<br />
Vybrid device block diagram is<br />
presented in the previous figure. The<br />
basic microarchitecture includes<br />
the dual-core structure interfacing<br />
to the network interconnect system<br />
bus fabric, providing the hardware<br />
interconnect matrix and supporting a<br />
64-bit third-generation ARM-AMBA<br />
Advanced eXtensible Interface split<br />
transaction protocol. This is followed<br />
Back to Table of Contents<br />
Vybrid Key<br />
Architecture Features ARM ® Cortex-A5 ARM Cortex-M4<br />
Instruction set architecture ARMv7-A ARMv7-ME, +-M4F (FPU)<br />
Architecture width 32 bits 32 bits<br />
Operating frequency<br />
relative to platform<br />
(2,3) x platform MHz 1x platform MHz<br />
Integer performance<br />
Microarchitecture<br />
1.57 DMIPS 2.1 per MHz 1.25 DMIPS 2.1 per MHz<br />
• Pipeline<br />
Eight stages<br />
Three stages<br />
• Instruction issue<br />
Limited superscalar (ALU + Br) Single<br />
• Execution units<br />
L1 processor, local memories<br />
• Capacity, organization<br />
VFPv3 (SP + DP FPU)<br />
NEON SIMD<br />
MMU, TrustZone<br />
I-Cache, D-Cache<br />
I-Cache = 32 KB,<br />
2-way SA<br />
D-Cache = 32 KB,<br />
4-way SA<br />
32 byte cache line size<br />
(4 beat, 64-bit burst)<br />
SPFPU<br />
v7-ME (DSP + SIMD)<br />
CodeCache, SystemCache,<br />
TCM (Lower, Upper)<br />
CodeCache = 16 KB,<br />
2-way SA<br />
SystemCache = 32 KB,<br />
2-way SA<br />
32 byte cache line size<br />
(4 beat, 64-bit burst)<br />
TCML(ower) = 32 KB<br />
TCMU(pper) = 32 KB<br />
Accesses from other<br />
masters via backdoor port<br />
L2 processor memories Optional L2 Cache<br />
• Capacity, organization L2-Cache = 512 KB,<br />
8-way SA<br />
32 byte cache line size,<br />
(4 beat, 64-bit burst)<br />
System bus interface 1x 64-bit AMBA3 AXI 2x 64-bit AMBA2 AHB-Lite<br />
On-chip RAM (OCRAM) Three 64-bit AXI ported memory controllers + arrays, 1.5 MB total<br />
• 2x system RAM (_sys) controllers, each 256 KB in capacity,<br />
512 KB total<br />
Optionally includes single-bit correction, double-bit detection<br />
(SECDED) ECC<br />
• 1x Graphics RAM (_gfx) Controller, 1 MB total<br />
512 Kbytes optionally used as L2 cache data array<br />
Programmable support for on-the-fly conversion of 16-bit<br />
pixel data to/from 32-bit ARGB8888<br />
DDR DRAM controller 2x 64-bit AXI input ports and 16-bit external DDR data bus<br />
Quad SPI memory controller 2x Quad SPI external memory controller<br />
FlexBus memory controller<br />
Gluelessly interfaces to external (non-DRAM) memories and/or<br />
ASICs, six chip selects<br />
by connections to a full complement of<br />
on-chip memories and slave peripherals<br />
connected via peripheral bridges as<br />
well as memory controllers for external<br />
interfaces including a multi-ported<br />
DDR DRAM controller, dual Quad SPIs<br />
and a FlexBus controller for glueless<br />
interfaces to simple (non-DRAM)<br />
memories and/or ASIC devices.
Back to Table of Contents<br />
ARM ® Cortex-A5 Processor Pipeline Organization 1<br />
Fetch 1 Fetch 2 Fetch 3<br />
ARM ® Cortex-M3 and ARM Cortex-M4 Pipeline<br />
For the standard configuration, Vybrid<br />
systems can best be characterized as<br />
a heterogeneous, symmetric, cachebased<br />
dual-core MPU architecture.<br />
The two ARM Cortex cores share<br />
an instruction set architecture with<br />
a common memory map, and the<br />
freescale.com/Vybrid<br />
Instruction ruc<br />
Queue ue<br />
Decode<br />
1 “ARM’s Midsize Multiprocessor, Next Cortex-A5 Supports<br />
Four-Way Coherent Multiprocessing,” Tom R. Halfhill,<br />
Microprocessor Report, 10/26/2009<br />
LSU branch<br />
result<br />
Fe De Ex<br />
Fetch<br />
Address<br />
Generation<br />
Unit<br />
Instruction<br />
Decode<br />
and<br />
Register<br />
Read<br />
Branch<br />
Address<br />
Phase<br />
and<br />
Writeback<br />
Shift<br />
Multiply<br />
and<br />
Divide<br />
Branch Forwarding<br />
and Speculation<br />
LU Branch No Forwarded/Speculated<br />
Issue<br />
Addr<br />
Gen<br />
Data<br />
Phase<br />
Load/<br />
Store<br />
and<br />
Branch<br />
ALU<br />
and<br />
Branch<br />
LSU Branch Result<br />
Mul1<br />
Shift<br />
Delta<br />
Cache<br />
1<br />
FP1<br />
address space is effectively accessible<br />
from either core. Memory coherency is<br />
wholly managed by software. There is<br />
hardware support for basic multicore<br />
requirements including peripheral<br />
interrupt steering plus directed<br />
CPU interrupts for inter-processor<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
WR<br />
Mul2<br />
ALU<br />
Delta<br />
Cache<br />
2<br />
FP2<br />
Writeback<br />
Writeback<br />
Writeback<br />
FP3 FP4 FP5<br />
communication, semaphores, run/<br />
halt/reset control, memory protection<br />
via ARM’s TrustZone architecture with<br />
<strong>Freescale</strong> security extensions and<br />
shared dual-core debug resources<br />
including cross-triggering capabilities.<br />
With significant amounts of both<br />
processor-local memories (L1 core<br />
caches, ARM Cortex-M4’s tightly<br />
coupled memories with its backdoor<br />
port for alternate bus master<br />
accesses, and the optional ARM<br />
Cortex-A5 512 KB L2 cache) and<br />
the SoC resources associated with<br />
on-chip RAM and boot ROM plus<br />
the controllers for the external DDR<br />
DRAM, Quad SPI (flash) memories<br />
and FlexBus, the Vybrid architecture<br />
is a high-performance dual-core<br />
implementation, providing rich<br />
applications in real time for a number<br />
of growing embedded application<br />
spaces.<br />
21
Technical Highlights<br />
Multicore Communication<br />
A flexible API for communicating between<br />
heterogeneous cores<br />
A multicore architecture brings new<br />
challenges to system design because<br />
the software must be rewritten to<br />
distribute tasks across the available<br />
cores. In addition, all the peripheral<br />
resources need to be properly<br />
allocated to avoid resource contention<br />
and share the data spaces between<br />
the cores efficiently.<br />
The Vybrid multicore solution with<br />
heterogeneous cores anticipates a<br />
customer running a high-level OS such<br />
as Linux on the ARM ® Cortex-A5<br />
and an RTOS such as <strong>Freescale</strong>’s<br />
MQX on the ARM Cortex-M4.<br />
Because of its real-time nature, the<br />
RTOS has a priority-based preemptive<br />
scheduler that is the heart of its<br />
task management services. These<br />
services could be communication and<br />
synchronization among tasks running<br />
on the same processor including<br />
messaging, semaphores, mutexes<br />
and event flags. A multicore SoC<br />
also needs mechanisms for reliable<br />
communication and synchronization<br />
among tasks running on different<br />
processing cores.<br />
22<br />
Multicore Communications Architecture<br />
ARM ® Cortex-A5<br />
(Linux ® )<br />
IPC API<br />
Transport Layer<br />
OS Specific Driver<br />
The Solution: Multicore<br />
Communication<br />
Data Path<br />
<strong>Freescale</strong>’s solution to the multicore<br />
architecture with different OSs is<br />
a multicore communication (MCC)<br />
protocol that takes maximum<br />
advantage of heterogeneous<br />
asymmetric multiprocessing (AMP)<br />
SoCs. It includes an easy-to-use API<br />
that can be easily extended to support<br />
additional operating systems and<br />
features.<br />
The MCC protocol is designed for low<br />
latency and low overhead operation<br />
and is optimized for embedded<br />
environments with constrained CPU<br />
and memory resources. To achieve this,<br />
the protocol is exclusively implemented<br />
using shared memory with no data<br />
translation or message headers.<br />
Data Path<br />
Shared Memory<br />
ARM ® Cortex-M4<br />
(MQX)<br />
IPC API<br />
Transport Layer<br />
OS Specific Driver<br />
Back to Table of Contents<br />
Multicore, multi-OS architecture provides shared memory and message-based communication paths.<br />
Applications communicate using a<br />
client-server methodology. To do this,<br />
each application participating on the<br />
separate OS creates a connection<br />
to a specific protocol port with one<br />
endpoint receiving data and the<br />
other sending data. In addition, each<br />
endpoint has its own associated<br />
port for each channel, similar to BSD<br />
sockets. To simplify the design, all<br />
communication is message-based and<br />
avoids connection-oriented or packetbased<br />
data streams. Messages can<br />
be queued on the receive end up to a<br />
configurable limit.<br />
As shown in the figure above,<br />
messages pass between endpoints<br />
via bidirectional connection-less<br />
communication channels.
Back to Table of Contents<br />
A tuple (node, port) uniquely identifies<br />
each endpoint. In addition, each<br />
independent thread of execution<br />
with a private memory space can<br />
operate as a node. This implies that<br />
a single-process RTOS like MQX will<br />
have, at most, one node. In contrast,<br />
a multi-process OS like Linux ® could<br />
contain one node per process. A port<br />
operates as a mailbox location where<br />
data can be delivered. Each node can<br />
utilize multiple ports and the same<br />
port can be used simultaneously by<br />
multiple nodes.<br />
Implemented as a user space library,<br />
the protocol includes an external<br />
API and transport layer. Supported<br />
operating systems include kernel<br />
components that allow the protocol to<br />
take advantage of <strong>Freescale</strong> hardware<br />
architecture features to synchronize<br />
shared memory access.<br />
Hardware Architecture<br />
The new heterogeneous AMP SoC<br />
includes several hardware features<br />
that allow optimal implementation of<br />
the MCC.<br />
The shared memory region used by<br />
all cores has two distinct areas: one<br />
for configuration and bookkeeping,<br />
and the other for data buffers.<br />
Hardware semaphores are used<br />
as the synchronization primitive to<br />
surround critical sections of code that<br />
access shared memory blocks. The<br />
hardware semaphore synchronization<br />
is required since each core is<br />
separately running an instance (or<br />
instances) of the MCC library.<br />
freescale.com/Vybrid<br />
CPU-to-CPU interrupts signal when<br />
new blocks are available for data<br />
sending and when data exists<br />
to be received. This mechanism<br />
implements the blocking versions of<br />
the message-send and messagereceive<br />
API calls.<br />
MCC Advantages<br />
The MCC solution utilizes shared<br />
memory as the data transport<br />
mechanism. This design minimizes<br />
communication latency by using<br />
zero-copy, so data passes by<br />
reference rather than physically<br />
being copied.<br />
A good example of where this low<br />
latency can provide significant<br />
application benefits is in network<br />
processing. With network processing,<br />
data transmission occurs frequently<br />
and in large quantities based on<br />
the high-bandwidth network traffic<br />
that Ethernet and proprietary<br />
communication protocols can deliver.<br />
MCC with zero-copy can off-load<br />
the network processing. In a typical<br />
application, the ARM Cortex-M4 core<br />
receives and processes complex<br />
network data and feeds the raw data<br />
back to the ARM Cortex-A5 core for<br />
use by an application.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Additional use cases that can take<br />
advantage of the Vybrid device<br />
capabilities include:<br />
• Segmenting real-time application<br />
code. This involves running realtime<br />
code on the ARM Cortex-M4<br />
core to operate independently of<br />
higher-latency code running on<br />
the ARM Cortex-A5 core. The new<br />
MCC can be used to share data<br />
between them<br />
• Off-loading CPU-intensive<br />
operations. An audio software<br />
platform may experiment with<br />
executing audio stream parsing and<br />
decoding on the ARM Cortex-M4<br />
core to improve the real-time<br />
responsiveness of the UI and other<br />
applications running on the ARM<br />
Cortex-A5<br />
• Minimizing power draw. The<br />
ARM Cortex-M4 core can be<br />
the primary component of the<br />
system during periods of low<br />
CPU utilization/idling and the<br />
ARM Cortex-A5 can be activated<br />
during periods of high-demand or<br />
for specific CPU-intensive tasks.<br />
This synchronization would be<br />
accomplished using <strong>Freescale</strong> MCC<br />
• Partitioning sensitive code for<br />
medical or safety reasons<br />
23
Technical Highlights<br />
Multimedia Subsystem<br />
Enabling rich apps with hardware acceleration<br />
The Vybrid multimedia subsystem<br />
consists of the video interface unit<br />
(VIU), display control unit, touch screen<br />
controller, segment LCD, OpenVG<br />
GPU and the audio subsystem.<br />
This multimedia subsystem helps<br />
to minimize and possibly eliminate<br />
the need for the cores to handle<br />
any pixels, allowing them to manage<br />
system level tasks.<br />
24<br />
Multimedia Block Diagram<br />
Display<br />
TFT LCD<br />
Touch Screen Controller<br />
Segment LCD<br />
Video<br />
Video Camera Interface<br />
Open VG GPU<br />
Audio<br />
ASRC<br />
SAI x 4<br />
ESAI<br />
SPDIF<br />
This section will describe the more<br />
complex IP in the multimedia<br />
subsystem and give a pictorial<br />
representation of the pixel processing<br />
of the subsystem.<br />
Video Subsystem<br />
VIU<br />
The VIU provides a 24-bit parallel<br />
interface for digital video. The VIU<br />
accepts ITU-R BT.565-compatible<br />
video, digital RGB and YUV444<br />
formats on its parallel interface,<br />
decodes it and optionally performs<br />
processes such as down-scaling,<br />
horizontal up-scaling, brightness<br />
and contrast adjustment, YUV to<br />
RGB conversion, deinterlacing and<br />
Multimedia Pixel Processing<br />
Digital<br />
Input<br />
Camera<br />
Image Signal<br />
Image Processing<br />
and Scaling<br />
Combining with Audio<br />
Audio Compression<br />
Back to Table of Contents<br />
horizontal mirroring. The resulting<br />
video stream is stored to system<br />
memory for subsequent postprocessing<br />
and displayed by a display<br />
control unit.<br />
The video subsystem supports both<br />
digital and analog inputs. In the case<br />
of digital video, the interface is directly<br />
into the VIU module either as RGB<br />
data or an ITU-R BT-565 compatible<br />
YUV data stream. For composite video<br />
the on-chip video analog decoder<br />
(video ADC) is required, the output of<br />
which will feed the VIU digital input.<br />
The input formats supported for<br />
composite video are PAL and NTSC<br />
and up to four input channels are<br />
muxed down to one ADC.<br />
Image Sensor Display<br />
Analog<br />
Input<br />
Video ADC<br />
Video Interface Unit (VIU)<br />
System Memory<br />
Memory<br />
Communication Network<br />
ARM<br />
Display Control Unit<br />
(DCU)<br />
RLE Decompression<br />
of Compressed Image<br />
in Memory<br />
Run Length Encoder (RLE)<br />
Lossless Decompression<br />
Separation from Audio<br />
Audio Decompression<br />
Display Enhancement<br />
Video/Graphics Combining<br />
Graphics<br />
Acceleration<br />
Rotation<br />
ColorSpace<br />
Conversion<br />
Graphic Processing Unit<br />
(GPU)<br />
Hardware Accelerated
Back to Table of Contents<br />
OpenVG GPU Subsystem Block Diagram<br />
AHB<br />
Features<br />
• Supports QVGA to XGA<br />
• Input options:<br />
8/10-bit ITU656 video<br />
Up to 24-bit digital RGB<br />
• Scaling:<br />
Command<br />
System<br />
Up to 1/8 video down-scaling with<br />
different scaling ratios in horizontal<br />
and vertical directions<br />
Up to 2x video up-scaling in<br />
horizontal direction<br />
• Brightness and contrast adjustment<br />
• YUV to RGB888 or RGB565<br />
conversion<br />
• De-interlace function<br />
OpenVG GPU<br />
The vector graphics processing is<br />
based on the Vivante GC355 core<br />
supporting the OpenVG1.1 API. Using<br />
a vector graphics core, Vybrid devices<br />
support applications that require flash<br />
acceleration or UI acceleration.<br />
Features<br />
• Real-time hardware curve<br />
tesselation of lines, quadratic and<br />
cubic Bezier curves<br />
• 16x line anti-aliasing<br />
• OpenVG 1.1 support<br />
• Vector drawing<br />
freescale.com/Vybrid<br />
Vector Graphics<br />
Pipeline<br />
Tessellation<br />
Engine<br />
GC355<br />
Texture +<br />
Gradient<br />
Unit and<br />
Cache<br />
Pixel<br />
Backend<br />
MMU<br />
System<br />
Interface<br />
Display Subsystem<br />
Display Controller Unit<br />
The display controller unit (DCU) is<br />
the interface to TFT LCD displays.<br />
It generates all the signals required<br />
to drive the display. Layer data is<br />
stored in on-chip or external memory<br />
and is fetched by the internal DMA<br />
channels of the DCU. The layer<br />
data is described using layer control<br />
descriptors that form part of the<br />
register set of the DCU.<br />
Features<br />
• Resolutions supporting up to XGA<br />
(1024x768)<br />
• Generates full RGB888 data and<br />
control signals for TFT display<br />
• Direct blitting engine with real time<br />
alpha-blending<br />
• Blending of each pixel using up to<br />
six source layers<br />
• Total of 64 graphics layers<br />
• Gamma correction with 8-bit<br />
resolution on each color component<br />
• Temporal dithering<br />
• Window feature allowing easy<br />
cropping and horizontal scrolling<br />
with low CPU overhead<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
AXI<br />
Audio Subsystem<br />
The audio subsystem has IP to<br />
provide options for everything from<br />
asynchronous sample rate conversion<br />
to a stereo transceiver that can receive<br />
and transmit digital audio.<br />
Synchronous Audio Interface<br />
Synchronous audio interfaces (SAI)<br />
are used to transfer audio data.<br />
The SAI supports full-duplex serial<br />
interfaces with frame synchronization<br />
such as I 2 S, AC97 and CODEC/ DSP<br />
interfaces.<br />
Features<br />
• Transmitter with independent bit<br />
clock and frame sync supporting<br />
one data line<br />
• Receiver with independent bit clock<br />
and frame sync supporting one data<br />
line<br />
• Word size programmable from 8- to<br />
32-bit<br />
• Asynchronous 64/32 x 32-bit FIFO<br />
for each transmit and receive data<br />
line<br />
25
Technical Highlights<br />
Enhanced Serial Audio Interface<br />
The enhanced serial audio interface<br />
(ESAI) provides a full-duplex serial<br />
port for communication with a variety<br />
of serial devices including industrystandard<br />
codecs, SPDIF transceivers,<br />
and other processors. The ESAI<br />
consists of independent transmitter<br />
and receiver sections, each section<br />
with its own clock generator.<br />
Sony/Philips Digital Interface<br />
The Sony/Philips Digital Interface<br />
module is a stereo transceiver that<br />
allows the processor to receive and<br />
transmit digital audio over it using<br />
the IEC60958 standard, consumer<br />
format.<br />
Features<br />
• SPDIF receiver<br />
Input sample rate measurement<br />
Supports the following sampling<br />
rates: 32, 44.1, 48, 64, 88.2 and<br />
96 kHz<br />
CD text support<br />
CS and U bit recovery<br />
• SPDIF transmitter<br />
One SPDIF output, IEC 60958<br />
consumer format<br />
CS bit support<br />
• Low-power mode<br />
SPDIF can be disabled to save<br />
power when not in use<br />
26<br />
Audio Subsystem Block Diagram<br />
ASRC<br />
External<br />
(Virtual) Clocks<br />
SAI3<br />
SPDIF<br />
Asynchronous Sample Rate<br />
Converter<br />
The incoming audio data may be<br />
received from various sources at<br />
different sampling rates. The outgoing<br />
audio data may have different<br />
sampling rates and it can also be<br />
associated to output clocks that are<br />
asynchronous to the input clocks. The<br />
asynchronous sample rate converter<br />
(ASRC) converts the sampling rate of<br />
a signal associated with an input clock<br />
into a signal associated to a different<br />
output clock. The ASRC supports<br />
concurrent sample rate conversion of<br />
up to 10 channels of about -120 dB<br />
THD+N.<br />
SAI2 SAI1 SAI0<br />
ESAI_FIFO<br />
ESAI<br />
Back to Table of Contents<br />
Legend<br />
Data/Control<br />
Audio I/F<br />
Audio Clocks<br />
Dedicated<br />
Audio<br />
Modules<br />
Features<br />
• Supports up to 10 channels split<br />
into up to three sampling rate<br />
conversion sets<br />
• Individual association of each<br />
channel to one of the sampling rate<br />
pairs<br />
• Designed for rate conversion<br />
between 32, 44.1, 48 and 96 kHz.<br />
The useful audio signal bandwidth is<br />
below 24 kHz<br />
• Other sampling rates in the range<br />
of 8 to 200 kHz are also supported,<br />
but with reduced audio performance<br />
• Automatic accommodation to slow<br />
variations in the incoming and<br />
outgoing sampling rates<br />
• ASRC has a disable mechanism to<br />
save power when not in use
Back to Table of Contents<br />
Security Subsystem<br />
Secure your applications in an insecure world<br />
Security is an increasingly<br />
important feature for industrial<br />
and consumer applications as the<br />
number of hacking incidents that<br />
expose sensitive information and<br />
unauthorized use of copyrighted<br />
content is on the rise. Helping to<br />
ensure secure applications is a<br />
high priority for the Vybrid platform.<br />
Sensitive information and digital rights<br />
management data can be stored in a<br />
protected manner and used, allowing<br />
e-commerce and advanced contentbased<br />
subscriber services.<br />
Security Block Diagram<br />
Security<br />
Crypytography Module<br />
(CAAM)<br />
Tamper Detect<br />
Secure RTC<br />
Real-Time Integrity<br />
Checker (RTIC)<br />
Secure RAM<br />
Secure Fuses<br />
Secure WDOG<br />
Secure JTAG<br />
freescale.com/Vybrid<br />
Security Subsystem:<br />
A Trusted Platform<br />
The foundation of a secure system<br />
consists of the hardware platform<br />
and the critical code that executes on<br />
that platform. This foundation is built<br />
with an on-chip ROM-based boot-up<br />
process that initiates validation of the<br />
platform, including the following tasks:<br />
• Examining key hardware elements<br />
to help ensure that they are<br />
functioning properly<br />
• Verifying the authenticity and<br />
integrity of the critical code that<br />
controls the overall operation of<br />
the system<br />
The boot process gains control of<br />
the system immediately after reset<br />
by executing known boot code that<br />
is resident in the on-chip ROM. After<br />
verifying the authenticity of a start-up<br />
script residing in external memory (i.e.,<br />
NOR or NAND flash) the boot process<br />
follows that script using established<br />
cryptographic techniques to validate<br />
the authenticity and integrity of the<br />
operating system code and data in<br />
external memory.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
More flexibility is achieved by using<br />
electrically programmable fuses to<br />
enable or disable particular system<br />
functions. For example, it is possible<br />
to configure a production version,<br />
security-enabled device so that<br />
the JTAG debug port is completely<br />
disabled. For early prototype devices,<br />
portions of the security system can be<br />
selectively disabled, allowing access<br />
to otherwise inaccessible areas of the<br />
device. Full flexibility between these<br />
two extremes is possible.<br />
Software that is security aware is<br />
imperative for those products that<br />
need security. Sensitive data in<br />
plaintext form must not appear on<br />
external data buses, and it should be<br />
restricted to the minimum number of<br />
data paths internal to the chip.<br />
High Assurance Boot<br />
The high assurance boot (HAB) feature<br />
in the system boot ROM protects the<br />
platform from executing unauthorized<br />
software (malware) during the boot<br />
sequence. Unauthorized software can<br />
enter the platform during upgrades or<br />
re-provisioning or when booting from<br />
USB/UART connections or removable<br />
devices. If permitted to gain control<br />
of the boot sequence, unauthorized<br />
software can be the attack vector for<br />
a variety of goals including exposing<br />
stored secrets, circumventing access<br />
controls to sensitive data, services or<br />
networks and re-purposing the<br />
27
Technical Highlights<br />
platform. HAB supports booting the<br />
device to a known initial state by<br />
using digital signatures to recognize<br />
authentic software and running<br />
software signed by the device<br />
manufacturer.<br />
In addition, HAB can protect the<br />
confidentiality of software during<br />
off-chip storage by decrypting the<br />
software loaded into RAM prior<br />
to execution. The figure to the<br />
right shows HAB encrypted boot<br />
supported on the Vybrid platform.<br />
The software image is encrypted<br />
using a secret key before being<br />
programmed on the off-chip memory<br />
(typically flash). During boot, HAB<br />
uses the same secret key (stored<br />
in hardware fuses not visible to the<br />
user) to decrypt the software image.<br />
Hardware Security<br />
Elements<br />
Vybrid platform security architecture<br />
includes the following hardware<br />
components:<br />
• Cryptography acceleration and<br />
assurance module<br />
Supports acceleration and<br />
off-loading for selected crypto<br />
algorithms<br />
Supports NIST SP800-90<br />
compliant hardware random<br />
number generator<br />
16K secure memory (automatic<br />
zeroization) with up to four<br />
independent partitions<br />
Supports AES, DES, 3 DES,<br />
ArcFour Symmetric key blog<br />
ciphers<br />
Supports MD5, SHA-1, SHA-224,<br />
SHA-256 hashing algorithms<br />
• Random number generation<br />
NIST compliant SP800-90<br />
Combination of a true random<br />
number generator and a<br />
pseudo-random number<br />
generator<br />
28<br />
Encrypted High Assurance Boot<br />
Encryption Using<br />
Secret Key<br />
SW Image<br />
Encrypt<br />
(AES)<br />
Encrypted<br />
SW Image<br />
Build Environment Device Boot<br />
Secret Key<br />
Manufacturing<br />
OTP Key<br />
CAAM (AES)<br />
• Real-time integrity checker<br />
Periodic check on system<br />
memory for unauthorized<br />
modifications<br />
Supports up to four memory<br />
regions<br />
Use SHA-1 or SHA-256 as<br />
hashing algorithm<br />
Once started, RTIC can only be<br />
stopped and restarted by trusted<br />
software<br />
• Secure non-volatile storage<br />
Secure non-rollover real-time<br />
counter<br />
Non-rollover monotonic counter<br />
Zeroizable 256-bit secret key<br />
Support for tampers<br />
• Tamper Detection<br />
Support for up to six external<br />
tamper detectors<br />
Active tamper detection<br />
Wire mesh tamper<br />
Voltage, temperature and clock<br />
tamper detectors<br />
Key Blob<br />
Flash<br />
OTP Key<br />
Back to Table of Contents<br />
Secret Key<br />
Decrypt<br />
(AES)<br />
Key Blob<br />
Decryption Using<br />
Secret Key<br />
Decrypted<br />
SW Image<br />
Decrypt<br />
(AES)<br />
Encrypted<br />
SW Image<br />
• TrustZone Address Space Controller<br />
Supports 2, 4, 8 or 16<br />
independent address regions<br />
Access controls are<br />
independently programmable for<br />
each address region<br />
Protects all AXI slave<br />
memories—DDR, on-chip SRAM<br />
All AHB slave memories,<br />
FlexBus, Quad SPI are protected<br />
by AHB equivalent address<br />
space controller<br />
• Other security sub-blocks<br />
Secure fuses (OTPs)<br />
Central security unit<br />
AHB TrustZone Controller<br />
Trust Zone Watchdog<br />
Secure JTAG Controller
Back to Table of Contents<br />
Power Management<br />
Programmable power options for performance<br />
and long battery life<br />
The Vybrid platform was designed with<br />
power efficiency as one of its main<br />
goals. To reduce current consumption,<br />
the design has:<br />
• Dynamic power management of<br />
core and peripherals<br />
• Software-controlled clock gating of<br />
peripherals<br />
• Multiple power domains and voltage<br />
scaling to minimize leakage in lowpower<br />
modes<br />
Vybrid devices have a power<br />
management unit supporting a variety<br />
of operating modes to optimize SoC/<br />
application power consumption.<br />
There are nine modes of operation<br />
to allow the user to optimize<br />
power consumption for the level of<br />
functionality needed as well as several<br />
wakeup sources for the power modes.<br />
A low-leakage wakeup unit has up<br />
to eight internal peripheral wake-up<br />
sources, as well as up to sixteen<br />
external pins for wakeups. Several<br />
wakeup sources are available in the<br />
lowest power mode: low-power timer,<br />
real-time clock, ADC, DAC and several<br />
pin interrupts. Depending on the<br />
requirements of the user application, a<br />
variety of stop modes are available that<br />
provide state retention, partial power<br />
down and/or full power down of certain<br />
logic and/or memory. I/O states are<br />
held in all modes of operation except<br />
power gated modes (LPSTOP1,<br />
LPSTOP2, LPSTOP3). I/O state for<br />
16 wakeup pads is still retained in<br />
power gated modes.<br />
freescale.com/Vybrid<br />
Modes of Operation<br />
Modes General Description<br />
General Description Normal Normal Recovery Recovery Method<br />
Method<br />
RUN<br />
RUN<br />
All functionality of Faraday is available<br />
All functionality of Vybrid platform is available N/A<br />
N/A<br />
WAIT CA5 and CA5 CM4 and cores CM4 Halted cores halted Interrupt Interrupt<br />
LPRUN 24MHz 24 operation, MHz operation, PLL Bypass PLL bypass Interrupt Interrupt<br />
ULPRUN<br />
ULPRUN<br />
STOP<br />
STOP<br />
LPSTOP3<br />
32/128 kHz operation, PLL off Interrupt<br />
32kHz /128kHz operation, PLL Off Interrupt<br />
Lowest power mode with all power retained,<br />
Lowest power mode with all power retained, RAM<br />
Interrupt<br />
RAM retention and LVD protection<br />
Interrupt<br />
retention and LVD protection<br />
64K RAM retention. I/O states held.<br />
64K (tbd)<br />
ADCs/DACs<br />
RAM retention.<br />
optionally<br />
I/O states held. ADCs/DACs<br />
Wake-up/Reset<br />
FPO power-gated. RTC Wakeup/Reset<br />
optionally power-gated. RTC functional. Wakeup from<br />
interrupts functional. Wakeup from interrupts<br />
LPSTOP2<br />
LPSTOP2<br />
16K RAM retention. I/O states held.<br />
16K (tbd) RAM retention. I/O states held. ADCs/DACs<br />
optionally ADCs/DACs power-gated. optionally RTC functional. power-gated. Wakeup from RTC<br />
interrupts functional. Wakeup from interrupts<br />
Wake-up/Reset<br />
Wakeup/Reset<br />
LPSTOP1 I/O states I/O states held. ADCs/DACs held. ADCs/DACs optionally powergated. optionally RTC<br />
Wake-up/Reset<br />
LPSTOP1 functional. powergated. Wakeup from RTC interrupts functional. Wakeup from Wakeup/Reset<br />
Battery All supplies interrupts OFF, SRTC, 32kXOSC ON, tampers and monitors<br />
POR<br />
Backup ON. All supplies OFF, SRTC, 32k XOSC ON,<br />
Battery Backup<br />
tampers and monitors ON.<br />
POR<br />
LPRUN and ULPRUN are part of RUN Mode and there are no separate modes.<br />
Features<br />
• Single 3.3V+/-10% supply voltage<br />
• High-power voltage regulator<br />
with an external ballast transistor<br />
generating internal 1.2V supply<br />
voltage, 1.2A capacity and<br />
quiescent current less than 1 mA<br />
• Ability to switch supply voltage<br />
down from 1.2 to 1.1V in lowpower<br />
modes to minimize power<br />
consumption<br />
• Soft start of main high-power<br />
regulator to minimize in-rush<br />
currents. Start-up time < 500 us<br />
• Low-power regulator: For Stop<br />
modes. 50 mA capacity and<br />
quiescent current < 50 uA<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Ultra-low power regulator: For<br />
LPStop modes. 10 mA capacity and<br />
quiescent current < 5 uA<br />
• Well bias generator to increase well<br />
by ~300mV to minimize leakage in<br />
low-power modes<br />
• Multiple power domains and power<br />
gating to minimize low-power<br />
consumption<br />
• Low voltage detection (LVD) on main<br />
supplies and 1.2V supplies<br />
• 16 wakeup pins for low-power<br />
wakeup<br />
• The single 3.3V supply is used in<br />
the system for I/O power with the<br />
exception of the DRAM interface.<br />
The DRAM interface power will<br />
be generated external to the<br />
Vybrid SoC<br />
29
Technical Highlights<br />
Power Domains<br />
The Vybrid SoC is divided into six<br />
power domains: PD 4:0 and Vbat.<br />
• PD4: Main power domain. Contains<br />
full platform, cores, peripherals,<br />
clocking, PLLs and main 24 MHz<br />
XOSC. This domain is power<br />
gated off during LPSTOP modes<br />
of operation to minimize leakage<br />
power<br />
• PD3: ADC-DAC domain: This<br />
domain can be optionally powered<br />
off in LPSTOP modes depending<br />
if powered, ADC and DAC<br />
conversions can be performed in<br />
LPSTOP modes<br />
• PD2: 48 KB SRAM power domain:<br />
This domain can be optionally<br />
powered off in LPSTOP modes<br />
depending on the amount of SRAM<br />
that needs to be maintained<br />
• PD1: 16 KB SRAM power domain:<br />
This domain can be optionally<br />
powered off in LPSTOP modes if no<br />
SRAM retention is required<br />
• PD0: Always-on logic domain: This<br />
domain is always powered on in<br />
LPSTOP modes. It has wakeup<br />
logic, 24 MIRC, 128 KHz IRC and<br />
the voltage regulators<br />
• VBat: Battery/RTC domain: Contains<br />
the SecureRTC, 32 kHz XOSC,<br />
tamper and monitors. Powered by<br />
a coin cell when the main power<br />
supply is switched off<br />
30<br />
PMU Block Diagrams<br />
3.3V<br />
LVDs<br />
POR<br />
Regulator<br />
Coin Cell<br />
HPreg<br />
1.2V<br />
External ballast<br />
LPreg<br />
1.2V<br />
Internal ballast<br />
ULPreg<br />
1.2V<br />
Internal ballast<br />
2.5V LDO I/O and Analog<br />
1.1V LDO Analog<br />
3.3V LDO<br />
1.1V LDO<br />
Back to Table of Contents<br />
Main Power Domain:<br />
Core, platform, memories,<br />
graphics, peripherals,<br />
clocks, PLLs<br />
ADC/DAC Domain:<br />
2x DAC, 2X ADC<br />
SRAM Domain1:<br />
48k SRAM<br />
SRAM Domain0:<br />
16k SRAM(tbc)<br />
Always-on Domain:<br />
Wakeup LPTim<br />
Battery Domain:<br />
SRTC, 32 kHz,<br />
Tampers, monitors<br />
PD4<br />
PD3<br />
PD2<br />
PD1<br />
PD0
Back to Table of Contents<br />
Ethernet Subsystem<br />
Real-time networked measurement and control<br />
Vybrid devices, depending on the<br />
particular family, have dual Ethernet<br />
controllers and an L2 switch. The<br />
dual Ethernet controller modules, in<br />
conjunction with an external Ethernet<br />
PHY, are used to add Ethernet<br />
connectivity. Hardware IEEE ® 1588<br />
time stamping provides precision<br />
clock synchronization for real-time<br />
control in networked automation, test<br />
and measurement applications. Midto<br />
high-end industrial applications<br />
typically use dual Ethernet controllers.<br />
One Ethernet MAC can be used to<br />
manage the control nodes while the<br />
other Ethernet MAC can be used to<br />
connect to a remote sever for control<br />
or for redundancy. Most industrial<br />
Ethernet options (i.e., Profinet IRT or<br />
Ethernet Subsystem<br />
Application I/F Application I/F<br />
freescale.com/Vybrid<br />
uDMA<br />
+ AHB I/F<br />
uDMA<br />
+ AHB I/F<br />
3<br />
0<br />
Profinet IRT+) require determinism,<br />
where IEEE 1588 is the enabling<br />
feature. Dual Ethernet with the L2<br />
switch allows daisy chaining which<br />
would otherwise need an expensive<br />
external switch. The function of the L2<br />
switch is to route packets from one<br />
Ethernet port to the other Ethernet<br />
port without any CPU intervention.<br />
Ethernet Subsystem<br />
Features<br />
• Dual 10/100 Ethernet MAC (MAC-<br />
NET)<br />
Hardware support for IEEE 1588<br />
standard for a precision clock<br />
synchronization protocol for<br />
networked measurement and<br />
control systems<br />
L2 Switch<br />
2<br />
1<br />
Receive<br />
FIFO<br />
Transmit<br />
FIFO<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Ethernet MAC<br />
TOE Functions<br />
TCP/IP<br />
Performance<br />
Optimization<br />
TCP/IP<br />
Performance<br />
Optimization<br />
Reduced media independent<br />
interface (RMII) support<br />
Interfaces with unified DMA<br />
Supports wakeup from lowpower<br />
mode through magic<br />
packets<br />
Multiple clock source options for<br />
time-stamping clock<br />
• L2 Ethernet switch<br />
3-port switch<br />
Supports two MAC-NETs<br />
Supports 64-bit Atlantic/FIFO<br />
ports<br />
IEEE 1588 support<br />
Fast cut-through mode<br />
QoS with eight queues per port<br />
Port mirroring<br />
Level 3 IP snooping<br />
Configuration<br />
Statistics<br />
Register Interface<br />
• Dual unified DMA<br />
RX Control<br />
CRC<br />
Check<br />
CRC<br />
Generate<br />
Pause<br />
Frame<br />
Terminate<br />
TX Control<br />
Pause<br />
Frame<br />
Terminate<br />
MDIO<br />
Master<br />
MII/RMII<br />
Receive<br />
Interface<br />
MII/RMII<br />
Receive<br />
Interface<br />
PHY<br />
Management<br />
Interface<br />
31
Technical Highlights<br />
32<br />
On-chip transmit and receive<br />
FIFOs<br />
Supports legacy buffer<br />
descriptor programming models<br />
and functionality<br />
Enhanced buffer descriptor<br />
programming model for new<br />
Ethernet functionality<br />
Ethernet Subsystem<br />
Clocking Options<br />
The Ethernet subsystem uses the<br />
following clocks:<br />
• Dedicated on-chip PLL with fixed<br />
multiplier to generate 50 MHz RMII<br />
Ethernet clock. This clock also<br />
comes as chip output and goes to<br />
off-chip Ethernet PHY<br />
• Optional externally-supplied 50 MHz<br />
RMII clock. This clock is used as<br />
the timing reference for the RMII<br />
interface<br />
• A time-stamping clock for the IEEE<br />
1588 timers<br />
IEEE 1588 Timers<br />
The Ethernet module includes a fourchannel<br />
timer module for IEEE 1588<br />
time stamping. The timer supports<br />
input capture (rising, falling or both<br />
edges) and output compare (toggle<br />
or pulse with programmable polarity).<br />
The counter is able to operate<br />
asynchronously to the Ethernet bus<br />
by using one of the clock sources.<br />
Ethernet Operation in<br />
Low-Power Modes<br />
Ethernet-Only Operation<br />
The Ethernet MAC supports magic<br />
packet detection that can generate a<br />
wakeup in low-power mode. During<br />
low-power operation:<br />
• The MAC transmit logic is disabled<br />
Adjustable Timer<br />
ENETn_ATPER<br />
Correction<br />
Counter<br />
ENETn_ATINC<br />
ENETn_ATINC<br />
[INC_COR]<br />
Counter<br />
Mod<br />
• The core FIFO receive/transmit<br />
functions are disabled<br />
• The MAC receive logic is kept in<br />
normal mode but it ignores all traffic<br />
from the line except magic packets<br />
Dual Ethernet and L2 Switch<br />
Operation<br />
In low-power STOP mode, the<br />
MAC stops immediately and freezes<br />
register values, state machines and<br />
external pins. During this mode,<br />
the Ethernet subsystem clocks are<br />
shut down. Coming out of STOP<br />
mode returns the Ethernet MAC<br />
to operating from the state prior to<br />
STOP mode entry.<br />
External<br />
Free-Running<br />
Counter<br />
ENETn_ATINC<br />
[INC]<br />
Back to Table of Contents<br />
ENETn_ATCR<br />
[SLAVE]<br />
To MAC<br />
Dual Ethernet and L2 Switch<br />
Bypassed<br />
In low-power STOP mode, the MAC<br />
stops immediately and freezes register<br />
values, state machines and external<br />
pins. During this mode, the Ethernet<br />
subsystem clocks are shut down.<br />
Coming out of STOP mode returns the<br />
Ethernet MAC to operating from the<br />
state prior to STOP mode entry.<br />
Battery Mode of Operation<br />
The Ethernet MAC does not support<br />
any standby mode of operation or a<br />
capability to operate on battery power<br />
in case the main supply fails. The<br />
MAC will be disabled during<br />
this mode.
Back to Table of Contents<br />
USB Subsystem<br />
Flexible USB connectivity with integrated PHY<br />
The USB subsystem in Vybrid devices<br />
is comprised of several blocks<br />
that together provide flexible USB<br />
functionality. The USB subsystem<br />
includes:<br />
• Dual USB On-The-Go (OTG)<br />
2.0 compliant controller (specific<br />
controller depends on the device).<br />
Options are: High-Speed (HS), Full-<br />
Speed (FS) and Low-Speed (LS)<br />
• Dual on-chip HS USB PHY<br />
• USB regulator<br />
USB Controller<br />
The USB controller is a USB<br />
2.0-compliant serial interface engine<br />
for implementing a USB interface. The<br />
USB controller provides USB host<br />
and device communications along<br />
with support for OTG operation. The<br />
controller supports HS, (480 Mbps),<br />
FS (12 Mbps) and LS (1.5 Mbps)<br />
data transfer rates. The registers and<br />
data structures are based on the<br />
enhanced host controller interface<br />
specification (EHCI) for USB standard.<br />
The USB OTG module can act as a<br />
host or device. The USB controller<br />
is programmable to support host or<br />
device operations under firmware<br />
control. On-chip HS PHY is used<br />
for the 60 MHz clock source to the<br />
controller. The USB controller provides<br />
control and status signals to interface<br />
with external USB OTG and USB<br />
host power devices. Customers can<br />
use these control and status signals<br />
on the chip interface and the I 2 C bus<br />
to communicate with external USB<br />
On-The-Go and USB host power<br />
devices. USB host modules must<br />
supply 500 mA with a 5V supply<br />
on its downstream port (referred to<br />
freescale.com/Vybrid<br />
USB OTG/HOST PHY Architecture<br />
BIAS<br />
PLL<br />
Common<br />
Block<br />
OTG<br />
as VBUS), however, the USB OTG<br />
standard provides a minimum 8 mA<br />
VBUS supply requirement. If the<br />
connected device attempts to draw<br />
more than the allocated amount of<br />
current, the USB host must disable the<br />
port and remove power. USB VBUS is<br />
not provided on-chip. The Vybrid SoC<br />
provides pins for control and status to<br />
an external IC capable of managing<br />
the VBUS downstream supply.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
HS/FS/LS<br />
Receivers<br />
Squelch/<br />
Disconnect<br />
Clock<br />
Buffers<br />
Receiver<br />
Transmitter<br />
Local Bias<br />
D+/D- Pull-up/<br />
Pull-down Logic<br />
HS/FS/LS<br />
Transmitters<br />
Single-Ended<br />
Receivers<br />
Analog Block<br />
HS/FS/LS<br />
Receivers<br />
Squelch/<br />
Disconnect<br />
Clock<br />
Buffers<br />
Receiver<br />
Transmitter<br />
Local Bias<br />
D+/D- Pull-up/<br />
Pull-down Logic<br />
HS/FS/LS<br />
Transmitters<br />
Single-Ended<br />
Receivers<br />
Analog Block<br />
Test<br />
Interface<br />
HS DLL<br />
Elasticity<br />
Buffer<br />
FS DPLL<br />
HS<br />
FS<br />
Transceiver<br />
MUX<br />
Test<br />
Interface<br />
HS DLL<br />
Elasticity<br />
Buffer<br />
FS DPLL<br />
HS<br />
FS<br />
Transceiver<br />
MUX<br />
SYNC<br />
Detector<br />
MUX<br />
FS/LS<br />
NRZI<br />
Decoder<br />
NRZI<br />
Encoder<br />
Bit<br />
Unstuffer<br />
Receive<br />
State<br />
Machine<br />
Transmit<br />
State<br />
Machine<br />
Bit<br />
Stuffer<br />
USB 1.1<br />
Transceiver<br />
FS/LS<br />
Digital Block<br />
SYNC<br />
Detector<br />
MUX<br />
FS/LS<br />
NRZI<br />
Decoder<br />
NRZI<br />
Encoder<br />
Bit<br />
Unstuffer<br />
Receive<br />
State<br />
Machine<br />
Transmit<br />
State<br />
Machine<br />
Bit<br />
Stuffer<br />
USB 1.1<br />
Transceiver<br />
FS/LS<br />
Digital Block<br />
Rx Shift<br />
and Hold<br />
Control<br />
Logic<br />
Tx Shift<br />
and Hold<br />
Rx Shift<br />
and Hold<br />
Control<br />
Logic<br />
Tx Shift<br />
and Hold<br />
For OTG operations, external circuitry<br />
is required to manage the host<br />
negotiation protocol (HNP) and session<br />
request protocol (SRP). External ICs<br />
that are capable of providing the OTG<br />
VBUS with support for HNP and SRP,<br />
as well as support for programmable<br />
pull-up and pull-down resistors on the<br />
USB DP and DM lines, are available<br />
from various manufacturers.<br />
33
Technical Highlights<br />
Features<br />
• Complies with USB specification<br />
rev 2.0<br />
• USB host mode<br />
Supports EHCI<br />
34<br />
Supports HS operation using<br />
internal on-chip HS PHY<br />
Supported by Linux ® and other<br />
commercially available operating<br />
systems<br />
• USB device mode<br />
Supports HS operation using<br />
internal on-chip HS PHY<br />
Supports FS/LS operation using<br />
internal HS PHY<br />
Supports one upstream facing<br />
port<br />
Supports six programmable,<br />
bi-directional USB endpoints,<br />
including endpoint 0<br />
• Suspend mode/low-power<br />
As host, firmware can suspend<br />
individual devices or the entire<br />
USB and disable<br />
Chip clocks for low-power<br />
operation<br />
Device supports low-power<br />
suspend<br />
Remote wakeup supported for<br />
host and device<br />
Integrated with processor doze<br />
and stop modes for low-power<br />
operation<br />
Start of Frame<br />
USB audio use cases require some<br />
sort of audio clock recovery capability.<br />
The Vybrid system USB OTG controller<br />
supports use of the start of frame<br />
(SOF) signal, which is generated at<br />
the start of a microframe in the USB<br />
2.0 HS protocol. This is a signal with<br />
a rate of 125 microseconds. When<br />
operating in full-speed mode, the SOF<br />
SOF Implementation on the Vybrid Platform<br />
USB OTG 0<br />
USB OTG 1<br />
USB0 SOF<br />
USB1 SOF<br />
signal has a rate of 1 ms pulse that<br />
asserts for 64 system clock cycles<br />
when the SOF token is detected on<br />
the USB bus and the USB controller is<br />
in device mode.<br />
In order to properly support USB audio<br />
isochronous asynchronous mode of<br />
operation, it is necessary to measure<br />
how many audio sample clock ticks<br />
occur between two consecutive<br />
occurrences of the SOF signal. This<br />
measurement is used to provide<br />
feedback to the USB audio source in<br />
order to speed up or slow down the<br />
audio sample delivery over the USB<br />
bus.<br />
This is the method of estimating the<br />
ratio between the USB host clock<br />
(SOF occurrences) and the Vybrid<br />
device local audio clock.<br />
The figure above shows the USB SOF<br />
connectivity with FlexTimer to enable<br />
this scheme.<br />
FTM0<br />
FTM1<br />
FTM2<br />
FTM3<br />
Back to Table of Contents<br />
64 Cycles<br />
Pulse<br />
Stretcher<br />
64 Cycles<br />
Pulse<br />
Stretcher<br />
1. The two SOF signals (one from each USB port) must be brought to two timer<br />
channels of one FlexTimer. This flexibility is provided in FTM2 and FTM3 as<br />
shown in figure.<br />
2. At least one of the SOF should be connected to one channel of a second<br />
FlexTimer. This will allow measuring of two sets of audio clock/SOF signals.<br />
To accommodate this, the USB0 SOF is connected to all FlexTimers.<br />
USB OTG/HOST PHY<br />
Architecture<br />
USB0 SOF_PULSE<br />
USB1 SOF_PULSE<br />
Audio Master Clock should also be provided as one of the clock options to FlexTimers.<br />
The USB OTG HS PHY is a HS/FS/<br />
LS USB 2.0 PHY, integrated with the<br />
controller.<br />
The USB OTG HS HY comprises two<br />
USB 2.0 transceiver sub-modules, one<br />
OTG sub-module and one common<br />
module shared between USB OTG<br />
and USB H1 channels.<br />
USB OTG PHY Features<br />
• Complete physical interface module<br />
for USB 2.0 On-the-Go<br />
• UMTI+ Level 3 specification compliant<br />
• Supports USB HS (480 Mbps), FS<br />
(12 Mbps) and LS (1.5 Mbps)<br />
• Host, slave and OTG dual role device<br />
operational modes of OTG port<br />
• Host modes of host port<br />
• Integrated self-calibrated<br />
termination resistors for HS mode<br />
and full set of pull-up/pull-down<br />
resistors defined by USB 2.0<br />
electrical requirements
Back to Table of Contents<br />
Memory Subsystem<br />
Flexible memory hierarchy for optimal code footprint,<br />
security and BOM cost<br />
Vybrid devices have multiple memory<br />
interface options. In addition to<br />
having up to 1.5 MB of on-chip<br />
SRAM for speedy code execution,<br />
Vybrid devices can interface to a<br />
variety of external peripherals and<br />
memories for system expansion<br />
and data storage. Dual Quad SPI<br />
interfaces with Execute-in-Place (XiP)<br />
support can interface with the latest<br />
flash memory. A secure digital host<br />
controller supports SD, SDIO, MMC<br />
or CE-ATA cards for in-application<br />
software upgrades as well as media<br />
files or adding Wi-Fi ® support. NAND<br />
flash and DRAM controllers with ECC<br />
support allow connection to a wide<br />
variety of memory types for critical<br />
applications. Battery-backed RAM is<br />
critical for secure systems to store<br />
authentication keys. Vybrid devices<br />
provide 16 KB of secure RAM and the<br />
platform provides 96 KB ROM for high<br />
assurance boot.<br />
The “Vybrid Memory Hierarchy”<br />
diagram illustrates the memory<br />
hierarchy of Vybrid devices and the<br />
various memory interfaces.<br />
freescale.com/Vybrid<br />
Tag 7<br />
(Optional)<br />
Vybrid Memory Hierarchy<br />
Tag 6<br />
0<br />
0<br />
Data<br />
7<br />
ARM ® Cortex-A5 Core Complex<br />
ITM + ETM + ETB + CTI<br />
FPU + NEON<br />
Inst<br />
Alu/ Q<br />
Mul Ld/Sc Shift<br />
Data uTLB<br />
STB<br />
D-$<br />
4 x 8K<br />
AXI System Bus<br />
TLB<br />
AXI-BIU<br />
PFU & Branch<br />
Predictor<br />
Inst uTLB<br />
L2 Cache Controller<br />
Vybrid DRAM Controller<br />
I-$<br />
2 x 16K<br />
NIC-301<br />
SDIO x2 NAND Flash DDRC Quad SPI x2 OCRAM<br />
_sys<br />
Network<br />
Inter-Connect<br />
(NIC)<br />
64-bit AXI<br />
64-bit AXI<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
64<br />
64<br />
Multi-Port<br />
Arbitration<br />
Arbitration<br />
Engine<br />
OCRAM<br />
_sys<br />
OCRAM<br />
_gfx<br />
TPIU<br />
DAP<br />
DRAM Memory Controller<br />
Command<br />
Queue<br />
Ordering<br />
Engine<br />
Write<br />
Queue<br />
Read<br />
Queue<br />
Transaction<br />
Processing<br />
Sequence<br />
Engine<br />
Performance<br />
and Power<br />
Tuning<br />
Registers<br />
RAM<br />
Array, 32k<br />
Tag/Data<br />
Arrays, 2x 8k<br />
ARM ® Cortex-M4<br />
Core Complex<br />
NVIC<br />
FPU<br />
CM4 CPU<br />
FPB<br />
DWT CTI<br />
AP Bus Matrix ITM<br />
System Bus Code Bus<br />
TCMU<br />
Sys-$<br />
Sys BIU Code BIU<br />
TCML<br />
Code-$<br />
RAM<br />
Array, 32k<br />
Tag/Data<br />
Arrays, 2x 8k<br />
64 64 64<br />
AHB System Bus AHB Code Bus AHB Backdoor Port<br />
Boot<br />
ROMx2<br />
DFI Interface DFI Interface<br />
FlexBus PBRIDGE<br />
PHY<br />
Interface<br />
DLL<br />
ECC<br />
Device<br />
Interfaces<br />
DRAM<br />
DDR3<br />
LPDDR2<br />
35
Technical Highlights<br />
Vybrid DRAM Controller<br />
The Vybrid DRAM controller offers<br />
connectivity with application interfaces<br />
on one side and DRAM memory on<br />
the other.<br />
Vybrid DRAM Features<br />
• Supports 8-bit and 16-bit DRAM<br />
memories<br />
• Supports two 64-bit AXI port slave<br />
interfaces<br />
• Support for synchronous and<br />
asynchronous modes<br />
• Supports components up to 8 GB<br />
• Supports LPDDR2 (S2 and S4) and<br />
DDR3<br />
Supported LPDDR2 grades:<br />
LPDDR2-800 and under<br />
Supported DDR3 grades:<br />
DDR3-800<br />
• ECC support (only for 8-bit DRAM<br />
interface)<br />
• DFI interface to PHY<br />
Quad SPI<br />
Vybrid device’s QuadSPI implements a<br />
Double Data Rate interface, enhanced<br />
read data buffering schemes, XiP<br />
and support for dual-die flashes.<br />
Quad serial flash memories with DDR<br />
interfaces are available on the market<br />
with throughput up to 66 Mbps<br />
peak data rates. With a dual Quad<br />
SPI architecture this is increased to<br />
132 Mbps. An enhanced read data<br />
buffering architecture, minimizes the<br />
latency impact of cache misses. Only<br />
the CPU will access the Quad SPI in<br />
the XiP mode of operation. The<br />
36<br />
Vybrid NAND Flash Controller Block Diagram<br />
boot_after_reset<br />
lpg_clk<br />
lps_clk<br />
reset_b<br />
IPS BUS CPU Access Bus<br />
boot_done<br />
Boot<br />
Control<br />
CMD<br />
Data<br />
Control<br />
Register<br />
Config<br />
Addr<br />
Dec.<br />
DMA<br />
Control<br />
boot_fail<br />
IPM DMA Bus<br />
boot_mode<br />
external serial flash can be used at<br />
runtime for data storage (graphics,<br />
fonts etc.). It can also contain the<br />
application code image that will be<br />
copied to external DRAM at boot.<br />
Residue<br />
Generation<br />
Control<br />
BCH Encoder<br />
Seven ECC<br />
Modes<br />
ECC Control<br />
BCH<br />
Decoder<br />
Quad SPI Features<br />
• Double data rate support for<br />
Spansion (data learning) and<br />
Macronix (DTR2 mode) serial flash<br />
• XiP<br />
• Multi-master buffering support<br />
• Up to four independent master<br />
channels<br />
• Support for dual-die packages with<br />
two chip selects<br />
SRAM<br />
Control<br />
Back to Table of Contents<br />
SRAM<br />
Buffer<br />
BUS<br />
SRAM Buffer<br />
9 KB<br />
NAND FLASH CONTROL<br />
EMB IF<br />
NAND Flash Controller<br />
The NAND flash controller (NFC)<br />
interfaces standard NAND flash<br />
devices with Vybrid devices and hides<br />
the complexities of accessing the<br />
NAND flash. It provides a seamless<br />
interface to both 8- and 16-bit NAND<br />
flash parts with page sizes of 512<br />
bytes, 2 kilobytes, 4 kilobytes and<br />
8 kilobytes.<br />
There are two specific use-cases for<br />
NAND flash usage with Vybrid devices.<br />
a) Boot from NFC: This allows systems<br />
to directly boot from external NAND<br />
memory. Bootloader may either<br />
reside in ROM or external NAND<br />
device while the OS kernel would be<br />
part of external NAND memory.<br />
irq<br />
NFC_IO[15:0]<br />
NFC_CLE<br />
NFC_ALE<br />
NFC_CEn<br />
NFC_RE<br />
NFC_WE<br />
NFC/R/Bn<br />
REQ<br />
IDLE<br />
GRT
Back to Table of Contents<br />
Secure Digital Controller<br />
For the cases where ROM includes<br />
the bootloader (most likely), the<br />
system will boot from ROM, jump<br />
to external NFC and continue<br />
loading the OS kernel. For the cases<br />
where a bootloader as well as OS<br />
kernel resides in the external NAND<br />
memory, system will switch to<br />
external NFC after ROM initialization.<br />
b) NFC for bootloader: After ROM<br />
initialization, system switches to<br />
external NAND device to load the<br />
bootloader.<br />
Features<br />
• NAND flash interface: 8-bit/16-bit<br />
• Supports all NAND flash products<br />
regardless of density/organization<br />
(with page sizes of 512+16B/2K+64<br />
B/4K+128B/4K+218B/8K)<br />
• Supports flash device commands<br />
such as page read, page program,<br />
reset, block erase, read status, read<br />
ID, copy-back, multi-plane read/<br />
program, interleaved read/program,<br />
random input/output and read in<br />
EDO mode, but is not limited to<br />
these commands<br />
freescale.com/Vybrid<br />
Enhanced Secure Digital Host Controller<br />
DMA<br />
Interface<br />
AHB Bus<br />
IP Bus<br />
Transceiver<br />
IP Gasket<br />
IP Bus<br />
• Two configurable DMA channels<br />
• Bypassable ECC mode, NFC<br />
supports 4/6/8/12/16/24/32-bit<br />
error correction<br />
Secure Digital Controller<br />
The SD host controller version<br />
provides an interface between the<br />
host system and SD, SDIO, MMC or<br />
CE-ATA cards. The module has a builtin<br />
transceiver as shown in the figure<br />
above. The SDHC acts as a bridge,<br />
passing host bus transactions to SD/<br />
SDIO/MMC/CE-ATA cards by sending<br />
commands and performing data<br />
accesses to/from the cards. It handles<br />
SD/SDIO/MMC/CE-ATA protocols at<br />
the transmission level.<br />
The SD card is designed to meet the<br />
security, capacity, performance and<br />
environmental requirements inherent<br />
in newly emerging audio and video<br />
consumer electronic devices. The<br />
physical form factor, pin assignment<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Card<br />
and data transfer protocol are forward<br />
compatible with the multimedia card<br />
with some additions.<br />
The Vybrid family has two SDHC<br />
controllers, supporting up to an 8-bit<br />
interface for high-speed MMC/SDIO<br />
cards.<br />
SDHC Features<br />
• Conforms to SD Host Controller<br />
Standard Specification version 2.0<br />
• Compatible with the MMC System<br />
Specification version 4.2<br />
• Compatible with the SD Memory<br />
Card Specification version 2.0<br />
• Supports high capacity SD memory<br />
card<br />
• Compatible with the SDIO Card<br />
Specification version 2.0<br />
• Compatible with the CE-ATA Card<br />
Specification version 1.0<br />
• Supports 1-bit/4-bit SD and SDIO<br />
modes, 1-bit/4-bit/8-bit MMC<br />
modes, 4-bit/8-bit CE-ATA devices<br />
• Up to 200 Mbps data transfer for<br />
SD/SDIO cards using four parallel<br />
data lines<br />
• Up to 416 Mbps data transfer for<br />
MMC cards using eigiht parallel data<br />
lines<br />
37
Technical Highlights<br />
FlexBus<br />
The FlexBus interface on the Vybrid<br />
devices is designed to gluelessly<br />
connect with up to six external<br />
devices. Each version has 8-, 16- and<br />
32-bit port sizes with configuration<br />
for multiplexed or non-multiplexed<br />
addresses and data buses.<br />
Features<br />
• Byte-, halfword-, word- and 16-byte<br />
line-sized burst transfers<br />
• Programmable burst and burst<br />
inhibited transfers selectable for<br />
each chip select and transfer<br />
direction<br />
• Auto-acknowledge feature<br />
Primary wait state counter up to<br />
63 clocks<br />
Optional secondary wait state<br />
counter<br />
Useful for interfacing to burst<br />
memories that have a long<br />
access time for the first beat of<br />
data, but can deliver subsequent<br />
data faster<br />
• Programmable address setup time<br />
with respect to the assertion of chip<br />
select<br />
• Programmable address hold time<br />
with respect to the negation of chip<br />
select and transfer direction<br />
Flexbus supports the connection to:<br />
• Flash<br />
• Smart LCDs<br />
• FPGAs<br />
• SRAM<br />
• PROM<br />
• EPROM<br />
• EEPROM<br />
38<br />
FlexBus Modes of Operation of Operation<br />
Non Muxed Mode<br />
FlexBus Key Features Customer Benefits<br />
Back to Table of Contents<br />
8-, 16-, 32- and 128-bit line sized transfers Maximize throughput according to the specific<br />
application<br />
Programmable burst and burst-inhibited transfers<br />
selectable for each chip select and transfer<br />
direction<br />
Optimized traffic patterns for each client in<br />
the bus<br />
Auto-acknowledge feature Increased flexibility and lower BOM costs in<br />
glueless external device connections<br />
Programmable address-setup time<br />
Programmable address-hold time<br />
Data Data Data Data<br />
Address Address Address Address<br />
Data and Address Have Separate Ports<br />
Muxed Mode<br />
Address Data Data Address<br />
Data and Address Are Interleaved on the Same Port<br />
Smart LCD Mode<br />
Data Data Data Data<br />
Data Is Sent Sequentially on One Port
Back to Table of Contents<br />
The universal asynchronous receiver/<br />
transmitter (UART) module in Vybrid<br />
devices allows for asynchronous,<br />
full-duplex serial communication in a<br />
variety of formats.<br />
Features of the UART include:<br />
• Standard mark/space non-return-tozero<br />
format<br />
• Supports IrDA 1.4 return-to-zeroinverted<br />
format<br />
• Supports ISO 7816 protocol for<br />
interfacing with SIM cards and<br />
smartcards (feature supported on<br />
one UART module only)<br />
• 13-bit baud rate selection with<br />
by-32 fractional divide<br />
• Programmable eight- or nine-bit<br />
data formats<br />
• Ability to select MSB or LSB to be<br />
first on the wire<br />
• Hardware flow control support for<br />
request to send and clear to send<br />
signals<br />
• Separate transmit and receive<br />
(feature supported on two UART<br />
modules only) FIFOs with DMA<br />
request capability<br />
ISO 7816 Support<br />
Two of the UART modules support<br />
the ISO 7816 standard, allowing<br />
communication with SIM cards and<br />
smartcards. This feature has the<br />
following characteristics:<br />
• Supports T=0 and T=1 protocols<br />
• Automatic retransmission<br />
of NACKed packets with<br />
programmable retry threshold<br />
• Supports 11 and 12 ETU transfers<br />
• Detects initial packet and automated<br />
transfer parameter programming<br />
freescale.com/Vybrid<br />
UART Transmit Logic<br />
UART Transmit Logic<br />
Module<br />
Clock<br />
ISO ISO 7816 7816 Timing Timing Diagrams Diagrams<br />
ISO 7816 Format without Parity Error (T=0)<br />
START<br />
BIT<br />
BIT 0<br />
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7<br />
PARITY<br />
BIT STOP<br />
BIT<br />
STOP<br />
BIT<br />
ISO 7816 Format with Parity Error (T=0)<br />
START<br />
BIT<br />
BIT 0<br />
ISO 7816 Format (T=1)<br />
START<br />
BIT<br />
Baud Rate Generator<br />
SBR12:0 BRFA4:0<br />
PE<br />
PT<br />
BIT 0<br />
M10<br />
M<br />
TXINV<br />
MSBF<br />
Parity<br />
Generation<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Universal Asynchronous Receiver/<br />
Transmitter<br />
A flexible approach to full-duplex serial communication<br />
Stop<br />
IRQ/DMA<br />
Logic<br />
Internal Bus<br />
SCI Data Register (SCID)<br />
Variable 12-bit Transmit<br />
Shift Register<br />
Shift Direction<br />
7816 Logic<br />
Infrared Logic<br />
Start<br />
Transmitter<br />
Control<br />
TXDIR<br />
SBK<br />
TE<br />
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7<br />
PARITY<br />
BIT<br />
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7<br />
PARITY<br />
BIT<br />
R485 Contol<br />
Loop Control To Receiver<br />
NACK<br />
ERROR<br />
STOP<br />
BIT<br />
TXD Pin Control<br />
Tx port en<br />
Tx output buffer en<br />
Tx input buffer en<br />
DMA Done<br />
TxD<br />
NEXT<br />
START<br />
BIT<br />
TxD<br />
DMA Requests<br />
IRQ Requests<br />
LOOPS<br />
RSRC<br />
RTS_B<br />
CTS_B<br />
NEXT<br />
START<br />
BIT<br />
STOP<br />
BIT<br />
NEXT<br />
START<br />
BIT<br />
39
Technical Highlights<br />
• Interrupt-driven operation with seven<br />
ISO-7816 specific interrupts:<br />
Wait time violated<br />
40<br />
Character wait time violated<br />
Block wait time violated<br />
Initial character detected<br />
Transmit error threshold<br />
exceeded<br />
Receive error threshold<br />
exceeded<br />
Guard time violated<br />
Variety of Communications<br />
Formats Available<br />
The UART offers a number of options<br />
for data size, format and transmission/<br />
reception settings. The variety of<br />
available options makes the UART<br />
capable of implementing a wide variety<br />
of serial communications protocols.<br />
Features<br />
• Eight- and nine-bit data formats<br />
supporting parity over all nine bits<br />
• MSB or LSB first on wire<br />
• Programmable transmitter output<br />
polarity<br />
• Programmable receiver input polarity<br />
FIFOs with DMA<br />
Request Capability<br />
The UART FIFOs reduce the frequency<br />
of CPU processing required by the<br />
UART.<br />
The DMA can be configured to<br />
transfer an entire packet of data and<br />
then interrupt the CPU when all bytes<br />
are received. This means the CPU can<br />
process the entire packet all at once<br />
instead of needing to stop the current<br />
program flow to move data bytes as<br />
they are received.<br />
The size of the FIFOs vary depending<br />
on the particular device and the<br />
specific UART. The Vybrid platform<br />
supports 16-byte FIFO on two UARTS<br />
(UART0 and UART1) and 8-byte FIFO<br />
on the other UARTS (UART2, UART3,<br />
UART4, UART5).<br />
UART UART Receive Receive Logic Logic<br />
Module<br />
Clock<br />
RxD<br />
LOOPS<br />
RSRC<br />
From<br />
Transmitter<br />
RxD<br />
SBR12:0 BRFA4:0<br />
RE<br />
RAF<br />
Baud Rate<br />
Generator<br />
Receive<br />
Control<br />
Receiver<br />
Source<br />
Control<br />
Active Edge<br />
Detect<br />
UART UART Data Data Formats Formats<br />
Infrared Logic<br />
Eight <strong>Bits</strong> of Data with LSB First<br />
START<br />
BIT<br />
BIT 0<br />
Internal Bus<br />
Stop<br />
Data Buffer<br />
Variable 12-bit Receive<br />
Shift Register<br />
Shift Direction<br />
PE Parity<br />
PT<br />
Logic<br />
Back to Table of Contents<br />
Start<br />
Wakeup<br />
Logic<br />
7816 Logic<br />
IRQ/DMA<br />
Logic<br />
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6<br />
ADDRESS<br />
MARK<br />
BIT 7 STOP<br />
BIT<br />
Eight <strong>Bits</strong> of Data with MSB First<br />
ADDRESS<br />
MARK<br />
START<br />
BIT BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0<br />
M<br />
M10<br />
LBKDE<br />
MSBF<br />
RXINV<br />
DMA Requests<br />
IRQ Requests<br />
To TxD<br />
START<br />
BIT<br />
Nine <strong>Bits</strong> of Data with LSB First<br />
ADDRESS<br />
MARK<br />
START<br />
BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 BIT 8 STOP<br />
BIT<br />
Nine <strong>Bits</strong> of Data with MSB First<br />
ADDRESS<br />
MARK<br />
START<br />
BIT BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1<br />
STOP<br />
BIT<br />
BIT 0<br />
START<br />
BIT<br />
STOP<br />
BIT<br />
START<br />
BIT<br />
START<br />
BIT
Software and Development Tools
Software and Development Tools<br />
<strong>Freescale</strong> Virtual Hardware Platform<br />
A rapid product development tool designed to<br />
accelerate software development<br />
Vybrid families support a wide variety<br />
of complex I/O controllers, display<br />
subsystems and communication<br />
interfaces while supporting a highly<br />
configurable multicore and multimemory<br />
programmer’s model. Vybrid<br />
families are designed to efficiently<br />
handle numerous applicationlevel<br />
design challenges as well as<br />
traditional real-time embedded tasks.<br />
This is where our virtual hardware<br />
platform provides an additional<br />
resource for managing the design and<br />
debug of your application.<br />
The virtual hardware platform brings<br />
many features found in standard<br />
desktop virtual machine environments<br />
to embedded customers who need<br />
a platform to accelerate software<br />
development. Unlike traditional<br />
modeling environments, this tool<br />
leverages a fast instruction set model<br />
that runs natively with no code<br />
conversion requirements between x86<br />
and ARMV7.<br />
42<br />
This is combined with broad system<br />
modeling techniques, resulting in a<br />
Vybrid device with an example EVB<br />
hardware environment that can be<br />
virtually represented on any Windowsenabled<br />
machine.<br />
Features<br />
• Single executable product that loads<br />
editable data-driven files<br />
Editable bootimages<br />
Peripheral parameters<br />
(e.g., target display screen<br />
parameters)<br />
Feature/mux configurations on<br />
select features (I/Os, UARTs,<br />
GPIOs)<br />
EVB memory sizes (editable<br />
virtual machine configuration<br />
files to set EVB memory)<br />
• Fast instruction execution for one or<br />
both ARM ® cores<br />
Full support for ARM<br />
Cortex-A5 and ARM<br />
Cortex-M4 cores as<br />
implemented in Vybrid families<br />
Code execution capable of<br />
running high-level operating<br />
systems (Linux ® or others) at<br />
chip-level performance or faster<br />
• Bridged peripheral support between<br />
host platform and embedded virtual<br />
machine<br />
File system on host machine can<br />
be mapped to embedded virtual<br />
machine file system<br />
– Allows rapid testing of board<br />
support/processor support<br />
packages<br />
– Allows rapid application<br />
development (JAVA,<br />
Android ® , Linux, MQX<br />
and others)
Back to Table of Contents<br />
Diagram of Virtual Hardware Platform<br />
Embedded VM: Laptop Boundary<br />
Embedded VM: EVB Boundary<br />
Embedded VM: eMPU Boundary<br />
Cache<br />
VM-Cores<br />
A5 M4<br />
System Visiblity<br />
Trace Data<br />
IDE Tool<br />
Plug-ins<br />
Ethernet nodes on host machine<br />
can be mapped to Ethernet<br />
nodes on virtual target (Ethernet<br />
bridging ability)<br />
Display controller output to host<br />
machine display<br />
– Leverage GUI development<br />
packages to develop and test<br />
HMI/UI applications, on virtual<br />
display controllers. Control<br />
one or two screens at the<br />
same time<br />
freescale.com/Vybrid<br />
SRAM<br />
Ethernet<br />
Memory<br />
Subsystem<br />
Display<br />
Control<br />
Comm<br />
System<br />
Serial<br />
Flash<br />
NAND<br />
Flash<br />
Virtual<br />
Comm Ports<br />
(UARTs)<br />
Serial interface input and capture<br />
– Configure test files to<br />
generate/receive serial<br />
communications for testing<br />
and validating code<br />
– Leverage virtualized UARTs in<br />
Windows to transmit/receive<br />
live data with model<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
DDR<br />
Ethernet<br />
VM Bridge<br />
File<br />
System/<br />
Bridge<br />
Windows<br />
Frame<br />
Buffer<br />
Frame<br />
Buffer<br />
Config<br />
Laptop<br />
Ethernet/Wi-Fi ®<br />
Laptop File System<br />
Laptop LCD<br />
Screen<br />
Internal/External<br />
Window<br />
Virtual<br />
Screen 1<br />
Window<br />
Virtual<br />
Screen 2<br />
Network<br />
• Advanced debugging features<br />
Industry-leading IDE support<br />
allows real-time debug, trace,<br />
and visibility to internal debug<br />
data providing enhanced<br />
application-level development<br />
Debug access available through<br />
Windows DLL extensions<br />
43
Software and Development Tools<br />
<strong>Freescale</strong> MQX Software Solutions<br />
Complimentary full-featured RTOS<br />
<strong>Freescale</strong> streamlines<br />
embedded design with<br />
a complimentary RTOS<br />
and software stacks<br />
The increasing complexity of<br />
industrial applications and expanding<br />
functionality of semiconductors<br />
are driving embedded developers<br />
toward solutions that combine proven<br />
hardware and software platforms. To<br />
help accelerate time to market and<br />
improve application development<br />
success, <strong>Freescale</strong> offers the MQX<br />
RTOS with TCP/IP and USB software<br />
stacks and peripheral drivers to<br />
ColdFire, ColdFire+ and Kinetis MCU<br />
customers at no additional charge.<br />
The combination of <strong>Freescale</strong> MQX<br />
software solutions and our silicon<br />
portfolio creates a comprehensive<br />
source for hardware, software, tools<br />
and services.<br />
44<br />
<strong>Freescale</strong> Comprehensive Solution Solution<br />
CodeWarrior<br />
Development<br />
Environment<br />
(MQX OS<br />
Aware)<br />
CodeWarrior<br />
Processor<br />
Expert<br />
MQX Design<br />
and<br />
Development<br />
Tools<br />
Third Party:<br />
IAR ®<br />
ARM ® , Keil<br />
(MQX OS Aware)<br />
Open Source<br />
BDM and<br />
Third Party:<br />
Emulator/Probe<br />
PC Hosted<br />
<strong>Freescale</strong> MQX Software Solutions<br />
Reducing Cost,<br />
Accelerating Success<br />
Demo Code Applications<br />
Application Tasks and<br />
Industry-Specific Libraries<br />
MQX RTOS<br />
Optional<br />
Services<br />
BDM/JTAG<br />
By providing complimentary<br />
<strong>Freescale</strong> MQX software solutions<br />
with its silicon products, <strong>Freescale</strong><br />
helps alleviate much of the initial<br />
software investment hurdle faced by<br />
embedded developers. Comparable<br />
full-featured software offerings may<br />
cost developers as much as $95,000<br />
(USD) in licensing fees.<br />
Ethernet<br />
(RTCS)<br />
File System<br />
Core Services MQX RTOS<br />
BSP/PSP<br />
On Device<br />
USB<br />
CAN<br />
MCU<br />
Customized<br />
Applications<br />
Back to Table of Contents<br />
Discrete<br />
Driver,<br />
Third<br />
Party<br />
and<br />
<strong>Freescale</strong><br />
Application<br />
Enablement<br />
Layer<br />
HAL<br />
Hardware<br />
According to recent research,<br />
development teams spend<br />
approximately 60 percent of their<br />
resources on software. Embedded<br />
projects based on 32-bit devices have<br />
a greater need for software reuse to<br />
manage development costs.
Back to Table of Contents<br />
MQX RTOS: MQX Customizable RTOS: Customizable Component Component Set Set<br />
The <strong>Freescale</strong> MQX RTOS and<br />
software stacks address these<br />
developer needs by providing a<br />
scalable, reusable platform that works<br />
across a wide range of <strong>Freescale</strong><br />
processor architectures, development<br />
tools and third-party software<br />
environments.<br />
freescale.com/Vybrid<br />
Name Services<br />
Queues Interrupts<br />
Partitions Utilities<br />
Messages<br />
Task<br />
Management<br />
Task Errors<br />
Lightweight<br />
Initialization<br />
Core Memory<br />
Events<br />
Semaphores<br />
Services<br />
CORE<br />
Watchdogs Mutexes<br />
Task Queue<br />
Automatic<br />
Timers<br />
Scheduling<br />
Task Creation<br />
RR and FIFO<br />
IPCs<br />
Formatted I/O<br />
Scheduling<br />
Exception<br />
Handling<br />
I/O Subsystems Kernel Log<br />
Logs<br />
AS-NEEDED<br />
<strong>Freescale</strong> MQX is deployed as<br />
production-ready source code,<br />
including communications software<br />
stacks and peripheral drivers, at no<br />
additional cost. <strong>Freescale</strong> MQX is<br />
provided with a commercial-friendly<br />
software licensing model, enabling<br />
developers to keep their source<br />
modifications while being able to<br />
distribute the required binary code.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Full Featured, Proven and<br />
Scalable<br />
The MQX RTOS has been the<br />
backbone of embedded products<br />
based on <strong>Freescale</strong> silicon for<br />
more than 15 years. MQX software<br />
deployment spans a broad range<br />
of market segments and leading<br />
manufacturers worldwide.<br />
The <strong>Freescale</strong> MQX RTOS offers<br />
powerful, preemptive real-time<br />
performance with optimized context<br />
switch and interrupt time, enabling<br />
fast, highly predictable response<br />
times. Its small, configurable size<br />
conserves memory space for<br />
embedded applications and it can be<br />
configured to take as little as 6 KB<br />
of ROM, including kernel, interrupts,<br />
semaphores, queues and memory<br />
manager.<br />
The <strong>Freescale</strong> MQX RTOS offers<br />
a straightforward application<br />
programming interface with a modular,<br />
component-based architecture that<br />
makes it very scalable. Components<br />
are linked in only if needed, preventing<br />
unused functions from bloating the<br />
memory footprint. Plug-ins, such<br />
as security, industrial protocols and<br />
graphical interfaces from <strong>Freescale</strong>’s<br />
strong network of partners, can also<br />
be added.<br />
45
Software and Development Tools<br />
Certifiable to Medical and<br />
Aerospace Standards<br />
Even if your application does not<br />
require formal certification, the<br />
robustness of MQX provides a<br />
trusted platform that has been<br />
proven in thousands of timecritical,<br />
sophisticated applications.<br />
For designs that do have a formal<br />
certification process to follow,<br />
MQX is an excellent choice. Past<br />
licensees have certified MQX-based<br />
applications to medical specifications<br />
(CFR 820.30 Part 21, IEC 60601-<br />
1) and the aerospace requirements<br />
listed under DO-178b. Safetycritical<br />
applications based on MQX<br />
include eye surgery equipment,<br />
drug injection equipment, radiation<br />
dose monitoring equipment, aircraft<br />
braking systems and aircraft<br />
navigation equipment.<br />
46<br />
RTCS Tower TCP/IP System StackModules<br />
RPC<br />
XDR<br />
Sockets<br />
*SSH<br />
*SSL<br />
NAT IP<br />
*XML *SMTP *POP3 HTTP<br />
RIP<br />
Back to Table of Contents<br />
SNMP<br />
Telnet FTP TFTP DNS SNTP Web Server<br />
(v1, v2)<br />
ICMP<br />
ARP<br />
BootP<br />
IP-E<br />
DHCP<br />
TCP UDP<br />
IPCP<br />
CIDR<br />
PPP<br />
IGMP<br />
PAP<br />
CHAP CCP LCP<br />
Ethernet Serial HDLC<br />
*SNMP<br />
(v3)<br />
*Denotes optional products<br />
Application Presentation Session Transport Network Data Link Physical
Back to Table of Contents<br />
<strong>Freescale</strong> MQX Add-on Software<br />
Real-Time TCP/IP Communication Suite<br />
(RTCS) Optional Components<br />
Available from<br />
Embedded Access Inc.<br />
NanoSSL and NanoSSH Software by<br />
Mocana Available from freescale.com/<br />
nanossl, freescale.com/nanossh<br />
PEG + Graphics Library<br />
Available from<br />
freescale.com/peg<br />
SEGGER emWin<br />
Graphics Library/GUI<br />
Available from SEGGER Microcontroller<br />
CANOpen Master/Slave for Embedded<br />
Devices<br />
Available from IXXAT, Inc.<br />
Industrial Network<br />
and Field Bus Protocols<br />
Available from IXXAT, Inc.<br />
SFFS Flash File System<br />
Available from Embedded Access Inc.<br />
<strong>Freescale</strong> eGUI: Graphical LCD Driver<br />
Available from<br />
freescale.com/egui<br />
MicroBrowsers<br />
Available from Motomic Software, Inc.<br />
OS Changer—Reuse Application on MQX<br />
Available from MapuSoft Technologies<br />
freescale.com/Vybrid<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Network management: Support for SNMP version 1 and 2 is built into RTCS. EAI offers MQX<br />
SNMPv3<br />
• XML parsing and framing: The MQX XML component enables your device to accept data in XML,<br />
as well as send data packaged in XML<br />
• Email communication: The MQX SMTP module provides your device with outbound email<br />
communication and MQX POP3 provides the capability to accept incoming email communication<br />
• NanoSSH: Provides privacy, authentication and ensures data integrity between a secure server<br />
and its clients<br />
• NanoSSL: Cyptographic protocols that provide security for communications over networks such<br />
as the Internet<br />
• Portable embedded GUI library designed to provide a professional-quality GUI for embedded<br />
systems applications<br />
• Small, fast and easily ported to virtually any hardware configuration capable of supporting<br />
graphical output<br />
• emWin is designed to provide an efficient, LCD controller-independent GUI for any application that<br />
operates with a graphical LCD<br />
• CANopen is a CAN-based higher layer protocol<br />
• Developed as a standardized embedded network with highly flexible configuration capabilities<br />
• Unburdens the developer from dealing with CAN-specific details such as bit-timing and<br />
implementation-specific functions<br />
• Profinet RT for I/O device<br />
• EtherNet/IP for adapter and scanner<br />
• Ethernet powerlink for managing and controlled nodes<br />
• EtherCAT for slave nodes<br />
• SERCOS III for slave devices<br />
• Precision time protocol IEEE ® 1588-2008 (v2)<br />
• SFFS is a safe flash file system that can support almost any NOR or NAND flash device<br />
• Provides a high degree of reliability and complete protection against unexpected power failure or<br />
reset events<br />
• Provides wear leveling, bad block handling and ECC K30C algorithms to ensure you get optimal<br />
use out of a flash device<br />
• Pre-integrated with the MQX RTOS: allows you to create a robust file system quickly for an embedded<br />
device using on-chip or on-board flash devices<br />
The complimentary <strong>Freescale</strong> embedded graphical user interface (eGUI) allows single-chip MCU<br />
systems to implement a graphical user interface and drive the latest generation of color graphics<br />
LCD panels with integrated display RAM and simple serial peripheral interface (SPI) or parallel bus<br />
interface.<br />
The uButterfly Browser runs on MQX and browses, parses and renders HTML/CSS content.<br />
• Browse HTML 4/CSS 2.1 Web pages<br />
• Enable dynamic HTML, active graphics and media<br />
• An optional SDK allows browsing embedded/instanced within C, C++ or Qt apps (available as a<br />
separate product)<br />
OS Changer is a C/C++ source-level virtualization technology that allows you to easily re-use your<br />
software developed for one OS on MQX, while providing real-time performance.<br />
Available OS Changer Porting Kits:<br />
• VxWorks Porting Kit<br />
• pSOS Porting Kit<br />
• Linux/POSIX Porting Kit<br />
• Windows Porting Kit<br />
• Nucleus Porting Kit<br />
• micro-ITRON Porting Kit<br />
47
Software and Development Tools<br />
<strong>Freescale</strong> Tower System<br />
A modular development platform<br />
Overview<br />
The <strong>Freescale</strong> Tower System is a<br />
modular development platform for<br />
8-, 16- and 32-bit MCUs and MPUs<br />
that enables advanced development<br />
through rapid prototyping. Featuring<br />
multiple development boards or<br />
modules, the Tower System provides<br />
designers with building blocks for entrylevel<br />
to advanced MCU development.<br />
Modular and Expandable<br />
• Controller modules provide easyto-use,<br />
reconfigurable hardware<br />
• Interchangeable peripheral modules<br />
(including communications,<br />
memory and graphical LCD) make<br />
customization easy<br />
• Open-source hardware and<br />
standardized specifications<br />
promote the development of<br />
additional modules for added<br />
functionality and customization<br />
Speeds Development Time<br />
• Open source hardware<br />
and software allows quick<br />
development with proven designs<br />
• Integrated debugging interface<br />
allows for easy programming and<br />
run control via standard USB cable<br />
48<br />
The <strong>Freescale</strong> Tower System<br />
Controller/Processor<br />
Module (MCU/MPU)<br />
• Tower MCU/MPU<br />
board<br />
• Works stand-<br />
alone or in<br />
Tower System<br />
• Features<br />
integrated<br />
debugging<br />
interface for easy<br />
programming<br />
and run control<br />
via standard<br />
USB cable<br />
Secondary<br />
Elevator<br />
• Additional and<br />
secondary serial<br />
and expansion<br />
bus signals<br />
• Standardized signal<br />
assignments<br />
• Mounting holes<br />
and expansion<br />
connectors for sidemounting<br />
peripheral<br />
Peripheral Module<br />
• Adds features and functionality<br />
to your designs<br />
• Interchangeable with other peripheral<br />
modules and compatible with all<br />
controller/processor modules<br />
• Examples include serial interface,<br />
memory, Wi-Fi ® , graphical LCD, motor<br />
control, audio, Xtrinsic sensing and high<br />
precision analog modules<br />
Back to Table of Contents<br />
Primary Elevator<br />
• Common serial<br />
and expansion bus<br />
signals<br />
• Two 2x80<br />
connectors on<br />
back side for easy<br />
signal access and<br />
side-mounting<br />
board (LCD<br />
module)<br />
• Power regulation<br />
circuitry<br />
• Standardized signal<br />
assignments<br />
• Mounting holes<br />
Size<br />
• Fully assembled<br />
Tower System is<br />
approx.<br />
3.5” H x 3.5” W x<br />
3.5” D<br />
Board Connectors<br />
• Four card-edge<br />
connectors<br />
• Uses PCI Express ®<br />
connectors<br />
(x16, 90 mm/<br />
3.5” long, 164 pins)<br />
Tower Plug-In (TWRPI)<br />
• Designed to attach to modules<br />
that have a TWRPI socket(s)<br />
• Adds features and functionality<br />
• Swappable with other TWRPIs<br />
• Examples include accelerometers,<br />
key pads, touch pads, sliders and<br />
rotary touch pads
Back to Table of Contents<br />
Tower System Modules<br />
Controller/Processor Modules (8-, 16-, 32-bit) freescale.com/TowerController<br />
Works stand alone or as part of Tower<br />
System<br />
Cost Effective<br />
• Interchangeable peripheral<br />
modules can be re-used with all<br />
Tower System controller modules,<br />
eliminating the need to purchase<br />
redundant hardware for future<br />
designs<br />
• Enabling technologies like LCD,<br />
Wi-Fi ® , motor control, serial and<br />
memory interfacing are offered offthe-shelf<br />
at a low cost to provide a<br />
customized enablement solution<br />
Take Your Design<br />
to the Next Level<br />
For a complete list of development<br />
kits and modules offered as part of the<br />
<strong>Freescale</strong> Tower System, please visit<br />
freescale.com/Tower.<br />
freescale.com/Vybrid<br />
Allows rapid prototyping<br />
Features open source debugging interface Provides easy programming and run control<br />
via standard USB cable<br />
Peripheral Modules freescale.com/TowerPeripheral<br />
Can be re-used with all Tower System<br />
controller modules<br />
Interchangeable peripheral modules: Serial,<br />
memory, graphical LCD, prototyping, sensor<br />
Tower Plug-Ins freescale.com/TWRPI<br />
Designed to attach to any Tower System<br />
module with a TWRPI socket(s)<br />
Eliminates the need to buy/develop redundant<br />
hardware<br />
Enables advanced development and broad<br />
functionality<br />
Adds features and functionality with little<br />
investment<br />
Swappable components Allows for design flexibility<br />
Elevator Modules freescale.com/TowerELEV<br />
Two 2x80 connectors Provides easy signal access and sidemounting<br />
board (i.e. LCD module)<br />
Power regulation circuitry Provides power to all boards<br />
Standardized signal assignments Allows for customized peripheral module<br />
development<br />
Four card-edge connectors available Allows easy expansion using PCI Express ®<br />
connectors (x16, 90 mm/3.5” long, 164 pins)<br />
Partner Modules<br />
Tap into a powerful ecosystem of<br />
<strong>Freescale</strong> technology alliances for<br />
building smarter, better connected<br />
solutions. Designed to help you<br />
shorten your design cycle and get<br />
your products to market faster, these<br />
technology alliances provide you with<br />
access to rich design tools, peripherals<br />
and world-class support and training.<br />
A number of partners have developed<br />
modules for the Tower System. Some<br />
examples include the i.MX515 ARM ®<br />
Cortex-A8 Tower Computer Module<br />
and StackableUSB I/O Device Carrier<br />
module from Micro/sys, as well as<br />
the rapid prototyping system (RPS)<br />
AM1 and FM1 modules from iMN<br />
MicroControl.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
Tower Geeks Online Community<br />
TowerGeeks.org is an online design<br />
engineer community that allows<br />
members to interact, develop designs<br />
and share ideas. Offering a direct<br />
path to explore and interact with other<br />
engineers designing with the Tower<br />
System, TowerGeeks.org is a great way<br />
to discuss your projects, post videos of<br />
your progress, ask questions through<br />
the forum and upload software. With<br />
updates through Twitter and Facebook,<br />
it’s easy to get involved.<br />
Follow Tower Geeks on Twitter<br />
twitter.com/towergeeks<br />
Visit <strong>Freescale</strong> on Facebook<br />
facebook.com/freescale<br />
49
Software and Development Tools<br />
Swell PEG Product Line<br />
Any LCD. Anywhere. PEG Software.<br />
Swell Software provides graphical<br />
user interface solutions for embedded<br />
devices. Swell’s PEG Pro, PEG+ and<br />
C/PEG product offering includes a GUI<br />
library for embedded development that<br />
works tightly with real-time operating<br />
systems. These development tools<br />
allow developers to lay out user<br />
interface screens and controls using<br />
the PEG library and external resources<br />
to generate C or C++ code.<br />
PEG software accelerates GUI design<br />
for embedded devices by allowing<br />
developers to create prototypes on<br />
a Windows ® or Linux ® based PC. It<br />
provides a complete visual layout and<br />
design tool to enable GUI design to<br />
take place in parallel to the embedded<br />
software/hardware development.<br />
The PEG WindowBuilder automatically<br />
generates C or C++ source code that<br />
is ready to be compiled and linked<br />
into any application, accelerating the<br />
deployment of the final product.<br />
Swell’s GUI software products work<br />
hand in hand with <strong>Freescale</strong> customers’<br />
real-time operating systems to<br />
incorporate LCD screens, display and<br />
input interfaces into future products.<br />
GUI Interface Technology<br />
PEG’s modular form enables a<br />
rapid development process. The<br />
core library interfaces to different<br />
50<br />
GUI Interface Technology<br />
RTOS<br />
Application Layer<br />
RTOS<br />
Driver<br />
PEG Library<br />
LCD Driver<br />
LCD Driver<br />
Input<br />
Driver<br />
Window Builder Technology<br />
PEG Pro PEG+ C/PEG<br />
• Screen transitions<br />
• Multiple alpha-blended<br />
windows<br />
• True anti-aliasing<br />
• Gradient manager<br />
• Open GL support<br />
• Written in C++<br />
real-time operating systems, input<br />
devices and LCD controllers by<br />
replacing the underlining driver.<br />
PEG WindowBuilder for<br />
Rapid Development<br />
WindowBuilder allows a designer to lay<br />
out each of the screens for a project<br />
through a simple-to-use interface.<br />
• Full WYSIWYG development<br />
• Runs on PC/Linux/X11 to allow<br />
proof of concept development<br />
• Multiple window updates<br />
• Alpha-blended images<br />
• Run-time image decoders<br />
and language resources<br />
• Custom widget integration<br />
• Dynamic themes<br />
• Written in C++<br />
Back to Table of Contents<br />
• Designed for small LCDs<br />
(QVGA)<br />
• Low color-depth<br />
• Very small footprint<br />
• Single window update<br />
• Multi-language capable<br />
• Written in ANSI C<br />
One of the smallest footprints and most efficient code bases available.<br />
Starting 225 KB<br />
Typical 225–250 KB<br />
Starting at 160 KB<br />
Typical 160–175 KB<br />
Starting at 90 KB<br />
Typical 90–110 KB<br />
• Enables hardware/software<br />
development to happen in parallel<br />
• Made available for free evaluation<br />
For more information visit<br />
freescale.com/peg.
Back to Table of Contents<br />
Timesys LinuxLink<br />
Embedded Linux ® product development made easy<br />
Timesys helps to eliminate the<br />
learning time, complexity and risk in<br />
building and maintaining embedded<br />
Linux ® devices. As a leader among<br />
embedded Linux solution providers,<br />
Timesys offerings are available for<br />
many <strong>Freescale</strong> processor families<br />
including ColdFire, Kinetis, i.MX,<br />
Vybrid and Power Architecture ® based<br />
products.<br />
Timesys offers the award-winning<br />
LinuxLink embedded development<br />
system, expert Linux support and<br />
experienced professional services to<br />
help development teams bring open<br />
source Linux-based products to<br />
market faster and cheaper.<br />
With a LinuxLink subscription for your<br />
<strong>Freescale</strong> processor, you can:<br />
• Quickly assemble and boot an initial<br />
embedded Linux image on your<br />
<strong>Freescale</strong> development kit.<br />
• Patch/configure/rebuild/update<br />
your custom Linux platform on your<br />
desktop with a properly installed<br />
and configured development<br />
environment.<br />
• Debug/tune the platform with<br />
common open source development<br />
tools and development libraries/<br />
utilities.<br />
• Obtain help with common<br />
development tasks via technical<br />
assistance and a rich library of<br />
Timesys-authored “How To”<br />
documentation.<br />
Key LinuxLink Components:<br />
Linux Kernel, Toolchain, Software<br />
Packages, Bootloader<br />
All Timesys Linux platforms are built<br />
and tested for compatibility with our<br />
freescale.com/Vybrid<br />
Timesys LinuxLink<br />
Linux Kernel and Drivers<br />
• Latest open-source kernels<br />
• ARM ® and other architectures<br />
• Extensive SoC/device support<br />
Development Tools/Libraries<br />
• Latest version of gcc, glibc, uClibc<br />
• Tested on all supported SoCs<br />
• Eclipse-based environment<br />
OS Apps and Middleware<br />
• Rich selection of packages<br />
• Networking, industrial, consumer<br />
• Pre-built, tested, supported<br />
Boot Loader<br />
• For supported reference platforms<br />
• Industry-standard U-Boot<br />
• Latest open-source code base<br />
LinuxLink Software Development Framework<br />
semiconductor partners’ suggested<br />
bootloader, saving time with initial<br />
board bring up.<br />
Factory Distribution Builder<br />
Timesys’s Factory Distribution Builder<br />
enables complete customization of<br />
your Linux platform and integration of<br />
third-party and proprietary software.<br />
Also includes innovative “advice”<br />
and “recommendation” engines to<br />
minimize mistakes.<br />
TimeStorm IDE<br />
TimeStorm’s powerful suite of<br />
application development tools expertly<br />
handles embedded chores like crosscompiling<br />
and remote debugging<br />
while including support for advanced<br />
features like profiling, testing and leak<br />
detection. And TimeStorm is built on<br />
the Eclipse IDE foundation, a platform<br />
already familiar to developers.<br />
Update Notifications<br />
As a LinuxLink user, you’ll only receive<br />
automatic notifications of updates<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
CHOOSE BUILD DEPLOY<br />
TimeStorm IDE (Eclipse)<br />
• Application development and debug<br />
• Fully integrated with Factory tools<br />
• Compatible with Eclipse ecosystem<br />
Factory Distribution Builder<br />
• Interactive UI with intelligent advice<br />
• Guides your selection of packages<br />
• Web (hosted) and desktop versions<br />
Work Orders<br />
Updates<br />
• Automatic kernel updates<br />
• Automatic middleware updates<br />
• Web-based and desktop notifications<br />
Support<br />
• Web-based<br />
• In-person<br />
• Extensive documentation<br />
Your Custom Tools (SDK)<br />
• gcc/C library/gdb<br />
• Relevant application libraries<br />
Your Custom Image (BSP)<br />
• Kernel/drivers<br />
• Root file system<br />
Ready to run on<br />
your hardware<br />
relevant to the Linux components used<br />
in your software.<br />
Unmetered Expert Linux Help<br />
As a LinuxLink subscriber, you’ll have<br />
access to responsive technical support<br />
from our expert engineers. Intuitive online<br />
support enables detailed information<br />
exchanges and allows you to submit,<br />
view and update requests, and access<br />
or reopen resolved requests.<br />
Get Your Free LinuxLink—<br />
Build Your Custom BSP/SDK<br />
in Minutes<br />
Register for a Free LinuxLink account,<br />
and assemble a Linux image that you<br />
can download and run on your board.<br />
Register at timesys.com/register.<br />
For more information about Timesys’s<br />
LinuxLink embedded Linux build<br />
system, visit timesys.com/linuxlink.<br />
51
Software and Development Tools<br />
CodeWarrior Development Studio<br />
Based on the Eclipse open development platform<br />
The CodeWarrior Development<br />
Studio for Microcontrollers V10.x<br />
integrates the development tools for<br />
the RS08, S08, ColdFire, ColdFire+,<br />
DSC, Kinetis, Qorivva, PX and<br />
Vybrid architectures into a single<br />
product based on the Eclipse open<br />
development platform. Eclipse offers<br />
an excellent framework for building<br />
software development environments<br />
and is becoming a standard<br />
framework used by many embedded<br />
software vendors.<br />
• Eclipse IDE 3.6<br />
• Build system with optimizing C/C++<br />
compilers for RS08, S08, ColdFire,<br />
ColdFire+, DSC, Kinetis, Qorivva<br />
and PX series Power Architecture ®<br />
cores and Vybrid devices<br />
• Extensions to Eclipse C/C++<br />
development tools (CDT) to<br />
provide sophisticated features to<br />
troubleshoot and repair embedded<br />
applications<br />
Device/Connection<br />
Change Wizard<br />
The Device/Connection Change<br />
Wizard allows a project to be<br />
re-targeted to a new processor in<br />
as few as six mouse clicks. Simply<br />
select a new device (from the same<br />
or a different architecture—RS08,<br />
S08, ColdFire, ColdFire+, DSC,<br />
Kinetis, Vybrid, Qorivva and PX series<br />
Power Architecture cores or Vybrid<br />
devices), select the default connection<br />
and the CodeWarrior tool suite will<br />
automatically reconfigure the project<br />
for the new device with the correct<br />
build tools and support files.<br />
52<br />
C/C++ Perspective<br />
Device/Connection Change Wizard<br />
Code Warrior Key Features Key Benefits<br />
Back to Table of Contents<br />
Device Connection Change Wizard Easily retarget project to a new processor<br />
Trace and profile support for on-chip trace<br />
buffers<br />
Sophisticated emulator-like debug capability<br />
without additional hardware<br />
LiveView Monitor registers, memory and global<br />
variables without stopping the processor<br />
<strong>Freescale</strong> Processor Expert Problems in hardware layer can be resolved<br />
during initial design phase
Back to Table of Contents<br />
Debug Perspective<br />
Processor Expert<br />
Processor Expert Key Features Key Benefits<br />
Graphical user interface Allows an application to be specified by the<br />
functionality needed<br />
Automatic code generator Creates tested, optimized C code tuned to<br />
application needs and the selected <strong>Freescale</strong><br />
device<br />
Built-in knowledge base Immediately flags resource conflicts and<br />
incorrect settings so errors are caught early<br />
in the design cycle<br />
Component wizard Allows the creation of user-specific hardwareindependent<br />
embedded components<br />
freescale.com/Vybrid<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Compiler<br />
• Assembler<br />
• Linker<br />
• Header files<br />
• Vector tables<br />
• Libraries<br />
• Linker configuration files<br />
Profiling and Analysis<br />
The CodeWarrior profiling and<br />
analysis tools provide visibility into an<br />
application as it runs on the processor<br />
to identify operational problems.<br />
• Supports architectures with<br />
on-chip trace buffers (RS08, V1<br />
ColdFire, ColdFire+, Kinetis and<br />
Vybrid)<br />
• Allows tracepoints to be set to<br />
enable and disable trace output<br />
• Able to step through trace data<br />
and the corresponding source<br />
code simultaneously<br />
• Allows trace data to be exported<br />
into a Microsoft ® Excel ® file<br />
Processor Expert<br />
<strong>Freescale</strong>’s Processor Expert is a rapid<br />
application design tool that combines<br />
easy-to-use component-based<br />
application creation with an expert<br />
knowledge system.<br />
• CPU, on-chip peripherals,<br />
external peripherals and software<br />
functionality are encapsulated into<br />
embedded components<br />
• Each component’s functionality<br />
can be tailored to fit application<br />
requirements by modifying the<br />
component’s properties, methods<br />
and events<br />
• When the project is built,<br />
Processor Expert automatically<br />
generates highly optimized<br />
embedded C-code and places the<br />
source files into the project<br />
For more information, visit<br />
freescale.com/CWMCU10.<br />
53
Software and Development Tools<br />
ARM ®<br />
Overview<br />
The ARM ® Development Studio<br />
5 (DS-5) is a complete suite<br />
of software development tools<br />
for ARM processor-based ASICs<br />
and standard devices, including<br />
<strong>Freescale</strong>’s Vybrid family. DS-5<br />
accelerates software development<br />
by providing an easy-to-use,<br />
integrated and validated toolchain.<br />
Key Features and Benefits<br />
• Support for all ARM processors<br />
• Integration with the industrystandard<br />
Eclipse IDE, which<br />
provides a large ecosystem of thirdparty<br />
plug-ins<br />
• Flexible C/C++ editor and project<br />
manager<br />
• Powerful C/C++ compilation tools<br />
• Debugger supports all phases of<br />
development from bootloader to<br />
kernel, and user space<br />
• Streamline Performance Analyzer<br />
provides system-wide profiling<br />
based on performance counters<br />
• Instant correlation of performance<br />
bottlenecks (cache misses,<br />
interrupts) and software execution<br />
• Fast simulator for ARM software<br />
development on the host computer<br />
with typical speeds above 250 MHz<br />
• Support and maintenance contract<br />
for one year<br />
54<br />
Development Studio 5 (DS-5)<br />
The reference software development tool suite for<br />
ARM ®<br />
powered platforms<br />
DS-5 Debugger and DSTREAM<br />
DS-5 Debugger<br />
The DS-5 Debugger brings together<br />
the convenience and productivity of<br />
integrated embedded development<br />
tools with the power and flexibility<br />
of open source tools for Linux ® and<br />
Android ® .<br />
The DS-5 debugger provides:<br />
• Debug of code generated by ARM<br />
and GNU Compile.<br />
• Advanced Session Control and<br />
System Views control multiple<br />
simultaneous debug sessions,<br />
to one or more targets, from one<br />
debugger perspective<br />
• Run and stop mode debugging of<br />
single-core and multicore devices<br />
Back to Table of Contents<br />
• Linux kernel and user space debug,<br />
including context awareness,<br />
process, and threads<br />
• Non-intrusive instruction trace<br />
including summarized profile<br />
• Conditional and scripted<br />
breakpoints<br />
For expert Linux users, DS-5 includes<br />
the traditional GDB command line<br />
interface for detailed control of<br />
target interactions and flexibility<br />
with scripting advanced debugger<br />
functions.
Back to Table of Contents<br />
Streamline: Timeline and Call Paths<br />
Call paths view shows the processor time<br />
spent on each call tree. A flat profiling report is<br />
generated for the selected call path, which enables<br />
you to focus the analysis on a process or thread.<br />
DSTREAM<br />
The ARM DSTREAM high<br />
performance debug and trace unit<br />
enables powerful software debug and<br />
optimization on any ARM processorbased<br />
hardware target.<br />
DSTREAM enables the connection of<br />
DS-5 Debugger to ARM processorbased<br />
devices via JTAG or serial-wire<br />
debug. It uses FPGA acceleration to<br />
deliver high download speeds and<br />
fast stepping through code on single<br />
and multi-processor devices and<br />
enables:<br />
• Run control debug and trace unit<br />
supporting all ARM processors<br />
• USB 2.0 and Ethernet interface<br />
allows direct and remote<br />
connections from the host PC<br />
• Code downloads at speeds of<br />
up to 2500 Kbps<br />
• JTAG clocks of up to 60 MHz<br />
provide fast software upload over<br />
the existing debug port<br />
• 16-bit wide trace capture at 300<br />
MHz DDR (600 Mbit/s per pin)<br />
freescale.com/Vybrid<br />
Timeline view shows process and thread<br />
information over time, matched to SoC<br />
performance counters. This enables you to<br />
spot thread deadlocks and inefficiencies,<br />
as well as hot spots in time.<br />
• Flexible trace clock positioning<br />
(relative to trace data)<br />
• Large 4 GB trace buffer enables<br />
long-term trace of fast targets<br />
Streamline<br />
Streamline is the Linux and Android<br />
performance analysis tool in DS-5.<br />
Through a small driver running on the<br />
target, Streamline captures the target’s<br />
performance information and displays<br />
it in an easy to understand graphical<br />
interface. Streamline includes:<br />
• Intuitive display of information<br />
ranging from system-wide<br />
performance counters to hot<br />
spots in the source code, making<br />
it easy for developers to identify<br />
performance bottlenecks, multithreading<br />
issues and general<br />
inefficient resource usage<br />
• Visualization tools to analyze percore<br />
performance metrics with<br />
threads and processes for optimal<br />
synchronization and concurrency of<br />
target’s resources<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Filtering capabilities to restrict the<br />
data set used by statistical reports<br />
over time and per-process, thread<br />
or call path<br />
• Call paths view shows the processor<br />
time spent on each call tree. A flat<br />
report is generated for the selected<br />
call path, which enables you to<br />
focus the analysis of a process or<br />
thread<br />
• Code View highlights the hot spots<br />
within a function by displaying the<br />
processor time spent on each<br />
line of source code and on each<br />
disassembly instruction<br />
• Streamline Capture Options dialogue<br />
enables you to select the right<br />
balance between granularity and<br />
information detail, and intrusiveness<br />
ARM C/C++ Compiler<br />
The ARM Compiler in DS-5<br />
Professional Edition is the only<br />
commercial compiler co-developed<br />
with the ARM processors and<br />
specifically designed to optimally<br />
support the ARM architecture. It is<br />
the industry standard C and C++<br />
compiler for building applications<br />
targeting the ARM, Thumb ® , Thumb-<br />
2, VFP, and NEON instruction<br />
sets found in the newer Cortex<br />
processor-based devices.<br />
ARM processors are designed to best<br />
execute code generated by the ARM<br />
Compiler. The ARM Compiler enables<br />
the new features in all the ARM<br />
processors. It supports building of<br />
Symbian OS, ARM Linux, and Android<br />
native applications and libraries, as<br />
well as bare-metal applications and all<br />
major RTOSs.<br />
Learn more at arm.com/ds5.<br />
55
Software and Development Tools<br />
IAR Embedded Workbench<br />
Powerful, reliable development tools<br />
Continuing a long-standing<br />
relationship with <strong>Freescale</strong><br />
<strong>Semiconductor</strong>, IAR Systems ® has<br />
announced that their flagship IAR<br />
Embedded Workbench ® for ARM ®<br />
product supports <strong>Freescale</strong>’s new<br />
Vybrid devices based on the ARM<br />
Cortex-A5 and ARM Cortex-M4<br />
cores. IAR Systems supports nearly<br />
the entire lineup of <strong>Freescale</strong> MCUs,<br />
including the S08, HCS12, ColdFire<br />
(and all its variants), the Kinetis MCUs<br />
based on an ARM Cortex-M4 core<br />
and now Vybrid devices. IAR Systems<br />
is proud to be allied with <strong>Freescale</strong><br />
in bringing cutting-edge devices and<br />
tools to our mutual customers.<br />
IAR Embedded Workbench for<br />
ARM is a highly efficient and<br />
independent toolchain that supports<br />
ARM architectures, including Vybrid<br />
devices. The Embedded Workbench<br />
for ARM includes IAR’s IDE, C/C++<br />
Compiler, Assembler and Linker to<br />
give you unparalleled performance.<br />
56<br />
IAR Embedded Workbench<br />
Back to Table of Contents
Back to Table of Contents<br />
• Ease of use. IAR Embedded<br />
Workbench for ARM has over<br />
2,500 example projects to help<br />
you get your project off the ground<br />
quickly. These examples are part<br />
of the installation and are provided<br />
free of charge.<br />
• Support for all ARM hardware.<br />
IAR Embedded Workbench for<br />
ARM includes support for the<br />
floating point DSP unit that is<br />
available in many ARM Cortex-M4<br />
cores. It also supports the ARM<br />
Cortex-A5 core and the NEON<br />
instruction set that is the heart of<br />
the Vybrid architecture.<br />
• Tight code generation. The code<br />
generated is highly optimized<br />
and IAR Systems encourages<br />
developers to try out one of the free<br />
versions (32 kB-limited KickStart<br />
version or the 30-day evaluation<br />
version) at iar.com/ewarm to<br />
compare it to other compilers.<br />
Prototype your code and see how<br />
much more efficient IAR is in your<br />
design.<br />
• An embedded compiler brings<br />
you full C++. IAR Embedded<br />
Workbench for ARM brings<br />
you full desktop C++ (including<br />
exception handling, multiple/virtual<br />
inheritance, etc.) to help you crosscompile<br />
code and use the bevy<br />
of test suites available for the PC<br />
to validate and verify your design<br />
before it goes into the board.<br />
freescale.com/Vybrid<br />
Developing your Vybrid device<br />
application is never easier than<br />
when you use IAR.<br />
• Integration to popular sourcecode<br />
control systems. If you are<br />
using Subversion or a Microsoft<br />
Visual Source Safe-compliant<br />
control system, you can use the<br />
Embedded Workbench for ARM<br />
to check code in and out of the<br />
system to speed your development<br />
process.<br />
• Kernel-aware debugging for most<br />
RTOSs. The C-SPY ® debugger is<br />
able to do task-aware debugging<br />
for many popular RTOSs including<br />
MQX, Micrium uC/OS-II and –III,<br />
SMX, CMX, Quadros, Sciopta,<br />
embOS, Express Logic’s ThreadX,<br />
Free/Safe RTOS and others. This<br />
awareness allows you to see what<br />
is happening in your RTOS at a<br />
glance.<br />
• Power debugging. IAR Systems<br />
has a unique power debugging<br />
feature that allows you to see the<br />
power being consumed by your<br />
board when the board is powered<br />
by a J-Link Ultra. Making your<br />
design power-efficient used to<br />
be the domain of only hardware<br />
engineers, but IAR gives the ability<br />
to software engineers as well.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
• Local support with global<br />
reach. IAR Systems has 10<br />
offices worldwide (including three<br />
in the United States) and each<br />
one is staffed with capable and<br />
experienced engineers who are<br />
ready to help you with any issues<br />
that arise. No other compiler<br />
vendor can claim to have nearly as<br />
much assistance readily available.<br />
When considering which toolchain to<br />
use in your Vybrid design, consider<br />
the one that was first to support<br />
Kinetis MCUs, first to support Vybrid<br />
devices, first in service and first in<br />
performance: choose IAR Embedded<br />
Workbench for ARM.<br />
For more information, please<br />
email info.us@iar.com.<br />
57
Software and Development Tools<br />
Atollic tools provide you with powerful<br />
features that reduce your development<br />
time and enable you to release a<br />
software product with higher quality<br />
with less effort.<br />
Atollic aims to provide an embedded<br />
systems toolset that covers all worktasks<br />
that embedded developers<br />
are doing on a day-to-day basis.<br />
The Atollic product portfolio not only<br />
covers great tools for editing, building<br />
and debugging but offers powerful<br />
solutions for team collaboration,<br />
system and code analysis as well as<br />
test automation.<br />
TrueSTUDIO ® : The Embedded<br />
Systems Development Tool for<br />
the Next Decade<br />
Atollic TrueSTUDIO is the premier<br />
C/C++ development tool for<br />
embedded systems development,<br />
with its unrivalled feature-set and<br />
unprecedented integration. In addition<br />
to the state-of-the-art editor, the<br />
optimizing C/C++ compiler and<br />
multiprocessor-aware debugger with<br />
tracing support, Atollic TrueSTUDIO<br />
also includes features for team<br />
collaboration, graphical modeling<br />
and design, code review and review<br />
meetings.<br />
TrueINSPECTOR ® : Improve<br />
Software Quality with Static<br />
Source Code Analysis<br />
Atollic TrueINSPECTOR is a tool<br />
for professional code analysis. The<br />
product performs static source code<br />
inspection and generates software<br />
metrics including code complexity<br />
measurements. The source code is<br />
validated against a database of<br />
58<br />
formal coding standards, and coding<br />
constructs that are known to be errorprone<br />
are detected automatically.<br />
Atollic TrueINSPECTOR supports the<br />
MISRA ® -C:2004 rule standard.<br />
TrueVERIFIER: Get Superior<br />
Software Quality with Embedded<br />
Test Automation<br />
Atollic TrueVERIFIER is a tool for<br />
advanced test automation. The<br />
product performs source code<br />
analysis and auto-generate unit-test<br />
suites that exercise an extensive<br />
set of different execution paths. The<br />
tool downloads the test cases and<br />
runs them in a target board with<br />
code coverage monitoring. Finally,<br />
Atollic TrueVERIFIER visualizes the<br />
test results and the achieved code<br />
coverage (MC/DC-level).<br />
Back to Table of Contents<br />
Atollic<br />
World-class tools for embedded systems development<br />
True Studio<br />
TrueANALYZER ® : Measure Test<br />
Quality with Dynamic Execution<br />
Flow Analysis<br />
Atollic TrueANALYZER is a tool for<br />
in-target measurement of test quality.<br />
The product performs system-level<br />
dynamic execution flow analysis and<br />
provides rigorous code coverage<br />
measurements. Atollic TrueANALYZER<br />
supports many types of code<br />
coverage analysis up to the level of<br />
modified condition/decision coverage<br />
(MC/DC-level), which is required by<br />
RTCA DO-178B (Level A) for flightcontrol-system<br />
software.<br />
For more information on Atollic tools,<br />
visit atollic.com.
Back to Table of Contents<br />
Multilink and Cyclone<br />
Debug interfaces and production programming<br />
P&E’s line of Multilinks and Cyclones<br />
are powerful solutions that cover the<br />
complete product cycle.<br />
USB Multilink Debug<br />
Interfaces<br />
P&E’s USB Multilinks are affordable,<br />
development-oriented interfaces that<br />
allow access to the debug interface on<br />
a target MCU from the user’s PC. The<br />
new Multilink Universal and Multilink<br />
Universal FX represent the next step<br />
forward for this very successful line<br />
of hardware interfaces. They each<br />
combine support, in a single interface,<br />
for many <strong>Freescale</strong> architectures,<br />
including: Vybrid, Kinetis, HCS08,<br />
RS08, HC(S)12, ColdFire+/V1, ColdFire<br />
V2-V4, Qorivva MPC55xx/56xx and<br />
DSC. The FX version also provides<br />
much higher communications speeds<br />
for some architectures (up to a 10x<br />
speed improvement), and can be used<br />
to power the target device. These<br />
“universal” Multilinks include ribbon<br />
cables to allow connections to all of<br />
the supported architectures. The user<br />
can simply flip open the hinged section<br />
on the Multilink case and install the<br />
appropriate ribbon cable.<br />
Multilink and Cyclone<br />
freescale.com/Vybrid<br />
Multilink Universal and Multilink<br />
Universal FX Features<br />
• Draws power from USB interface—<br />
no separate power supply required<br />
• Target voltage: 1.6–5.25V<br />
• Includes a ribbon cable for each<br />
supported architecture<br />
• High-speed download (FX version)<br />
• Can provide target power (FX version)<br />
Supported Architectures<br />
• Vybrid<br />
• Kinetis<br />
• ColdFire+, ColdFire V1–V4<br />
• HCS08, RS08, HC(S)12<br />
• DSC<br />
Software Support<br />
• CodeWarrior IDE<br />
• P&E software (including<br />
programmers and debuggers)<br />
• Software tools from IAR, Keil,<br />
Mentor Graphics, Cosmic,<br />
and others. Support varies by<br />
architecture. Contact vendor to<br />
determine compatibility.<br />
Cyclone Production<br />
Programmers<br />
P&E’s Cyclone products are geared<br />
towards in-circuit production<br />
programming, including both<br />
low-volume, operator-controlled<br />
programming and high-volume<br />
automated programming. The Cyclone<br />
can be used to program both internal<br />
memory on a <strong>Freescale</strong> processor/<br />
MCU as well as external memory<br />
connected to the processor’s address/<br />
data bus. The processor can be<br />
mounted on the final printed circuit<br />
board before programming and does<br />
not need to be pre-programmed.<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
When connected to a PC, the Cyclone<br />
can communicate via USB, Ethernet,<br />
or serial port, and its operations can<br />
be completely automated. In standalone<br />
mode, programming images are<br />
first loaded into on-board memory.<br />
An LCD screen and buttons allow<br />
one-touch programming operation<br />
as well as configuration. P&E offers<br />
automation software packages<br />
allowing many Cyclone units to be<br />
“ganged” together.<br />
The Cyclone may also be used as a<br />
hardware interface with many popular<br />
debuggers, similar to the way a USB<br />
Multilink is used, but also including<br />
support for Ethernet and serial<br />
connections.<br />
Cyclone Features<br />
• Stores multiple images for<br />
programming<br />
• Can be fully automated and<br />
controlled from a PC<br />
• Can be controlled via buttons/<br />
display without a PC<br />
• Display for image selection, status,<br />
and settings<br />
• Can provide/switch power to target<br />
• High-speed programming<br />
• Multiple units may be “ganged” for<br />
parallel programming<br />
• Support for dynamic data, including<br />
serialization<br />
• May be used as a debug interface<br />
with many debuggers<br />
For more information, visit<br />
pemicro.com.<br />
59
Software and Development Tools<br />
Designed using SEGGER’s industryleading<br />
embedded software, J-Link<br />
debug probes offer a wide array of<br />
advanced features and boast support<br />
for a broad spectrum of MCUs and<br />
MPUs, including <strong>Freescale</strong>’s complete<br />
i.MX, Kinetis and ColdFire V2–V4<br />
lines. Many popular IDEs such as<br />
CodeWarrior, IAR, Keil, Code Sourcery<br />
V2–V4 and more have built-in support<br />
for the J-Link.<br />
The J-Link debug line offers a high<br />
download speed into RAM* and flash<br />
memory. Each JTAG debugger hardware<br />
model has its own unique attributes and<br />
offers a number of available software<br />
add-on modules to enhance the J-Link’s<br />
functionality. For more details, visit<br />
segger.com/jlink.html.<br />
J-Flash is a comprehensive user<br />
interface for flash programming. The<br />
flash breakpoint add-on allows for<br />
an unlimited number of breakpoints<br />
while debugging in flash memory. The<br />
J-Link SDK is a standard Windows<br />
DLL typically used from C. It makes<br />
the entire functionality of the J-Link<br />
available through the exported<br />
functions and allows you to write your<br />
own program using J-Link.<br />
Hardware Models<br />
J-Link Pro for Connectivity<br />
J-Link Pro is an enhanced version of<br />
the J-Link. It incorporates an on-board<br />
Ethernet interface in addition to the<br />
USB, as well as two LED hardware<br />
status indicators. It comes with licenses<br />
for all J-Link related SEGGER software<br />
products, including flash breakpoints,<br />
60<br />
RDI, J-Flash and GDB Server, providing<br />
the optimum debugging solution for the<br />
professional developer.<br />
J-Link ULTRA for High Performance<br />
J-Link ULTRA is based on the highly<br />
optimized and proven J-Link. It offers<br />
even higher speed as well as target<br />
power measurement capabilities due to<br />
the faster CPU, built-in FPGA and High-<br />
Speed USB interface. This permits you<br />
to take full advantage of the low power<br />
features offered by today’s modern<br />
cores. J-Link Ultra raises the bar, aiming<br />
to be the fastest emulator available.<br />
J-Trace for Cortex-M for<br />
Post-Mortem Analysis<br />
J-Trace for ARM ® Cortex-M is a<br />
JTAG probe which includes trace (ETM)<br />
support. J-Trace assists the developer<br />
in analyzing his target system’s<br />
behavior. The 4 MB trace memory<br />
provides plenty of space to store the<br />
last executed functions. This allows you<br />
to find out how the program arrived at a<br />
certain position in code, which is either<br />
not expected or wanted.<br />
Back to Table of Contents<br />
SEGGER: J-Link and Flasher<br />
Convenient development and production programming<br />
*The regular J-Link performs with an already high<br />
750 Kbps, J-Link Ultra allows an even faster peak<br />
download speed of 1.5 Mbps<br />
SEGGER Debug Probes and Production Flash Programmer<br />
J-Link<br />
Intelligent<br />
Debugging via<br />
JTAG/SWD<br />
• Robust communication<br />
• Very high performance<br />
(download speed up to 1.5 MB)*<br />
• Unlimited flash breakpoints<br />
(license required)<br />
Flasher for Production Flash<br />
Programming and in the Field<br />
Services<br />
The in-circuit programmer (Flasher<br />
ARM) is a superset of the J-Link DDL.<br />
It contains all of the debug probe<br />
features, while being designed for use<br />
in a production environment. Different<br />
interfaces, like the command line<br />
interface or the optionally available<br />
SDK, allow an easy integration into any<br />
production environment.<br />
The Flasher ARM has on-board<br />
memory to store your binary image,<br />
permitting simple stand-alone flash<br />
programming. This is particularly useful<br />
for support teams that have to upgrade<br />
devices out in the field. They only need<br />
to carry a small box which is readily<br />
configured to perform the update once<br />
it is connected to the target system.<br />
For more details, visit segger.com/<br />
flasherarm.html.
Back to Table of Contents<br />
SEGGER offers a feature rich, high<br />
performance RTOS, GUI, and family<br />
of middleware (file system, USB host<br />
and device, IP stack), all of which<br />
adhere to strict, yet efficient coding<br />
and documentation standards. The<br />
software is very easy to use and works<br />
out of the box. BSPs and projects for<br />
popular eval boards and tool chains are<br />
available, including BSPs for the popular<br />
<strong>Freescale</strong> based designs. SEGGER<br />
offers very flexible license models to<br />
meet any size project’s needs.<br />
Embedded Graphics<br />
Package (emWin)<br />
emWin is a professional graphical<br />
user interface (GUI) for any application<br />
that operates with a graphical LCD.<br />
For fast user interface development<br />
emWin provides a GUI-Builder software<br />
and an extensive widget selection.<br />
emWin is part of SEGGER’s complete<br />
middleware solution. Additionally,<br />
emWin is compatible with; polled,<br />
single-task, and multitask environments,<br />
with a proprietary operating system<br />
or with any commercial RTOS. It is<br />
shipped as C source code and may<br />
be adapted to any size physical and<br />
virtual display with any LCD controller<br />
and CPU. emWin can be optimized to<br />
run on very low resources. For more<br />
details, visit segger.com/emwin.html.<br />
RTOS (embOS)<br />
embOS is a priority-controlled real time<br />
operating system, designed to be used<br />
as a foundation for the development<br />
of embedded real-time applications.<br />
It is a zero interrupt latency (high<br />
priority interrupts are never disabled<br />
by embOS), high-performance RTOS<br />
that has been optimized for minimum<br />
memory consumption in both RAM<br />
freescale.com/Vybrid<br />
and ROM, as well as high speed and<br />
versatility. Throughout the development<br />
process of embOS, the limited<br />
resources of MCUs have always been<br />
kept in mind. The internal structure<br />
of embOS has been optimized for<br />
a variety of applications for different<br />
customers, to fit the needs of different<br />
industries. embOS is fully sourcecompatible<br />
on different platforms<br />
(8/16/32-bit), making it easy to port<br />
applications to different CPUs. Its’<br />
highly modular structure ensures that<br />
only those functions that are needed<br />
are linked, keeping the ROM size very<br />
small. We took full advantage of our<br />
partnership with <strong>Freescale</strong> by utilizing<br />
their expertise and knowledge of their<br />
hardware while adding support for<br />
Vybrid devices. This permits you to take<br />
full advantage of our software offering<br />
while being assured that it has been<br />
developed to the highest standards<br />
and optimized to the fullest. For more<br />
details, visit segger.com/embos.html.<br />
Embedded USB Stacks<br />
(emUSB-Device and<br />
emUSB-Host)<br />
emUSB-Device has been designed to<br />
work on any embedded system with a<br />
USB device controller. Ports for most<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
SEGGER: RTOS, GUI and Middleware<br />
Embedded software for the professional developer<br />
SEGGER RTOS, GUI and Middleware<br />
common USB devices are available. It<br />
can be used with USB 1.1.or USB 2.0<br />
Full- and High-Speed devices. emUSB<br />
supports, among others, the HID,<br />
CDC, MSD, MSD-CDROM, printer and<br />
custom bulk communication classes.<br />
emUSB-Host is the counterpart of<br />
emUSB-Device and supports HID,<br />
CDC (and FTDI), MSD, printer and<br />
custom bulk communication classes.<br />
Embedded IP Stack<br />
(embOS/IP)<br />
embOS/IP is a TCP/IP stack that<br />
provides a small memory footprint<br />
for high-performance embedded<br />
networking solutions. The stack has<br />
been optimized for use in real-time,<br />
memory-constrained embedded<br />
systems. It offers RFC-compliant TCP/<br />
IP and a standard socket API. embOS/<br />
IP works seamlessly with the embOS<br />
operating system. Additional higher<br />
level protocols like SMTP, FTP and<br />
HTTP are also available. On the link<br />
layer, embOS/IP supports PPP to ease<br />
the integration of M2M-communication.<br />
For more details, visit segger.com/<br />
embedded-software.html.<br />
61
Software and Development Tools<br />
Lauterbach<br />
TRACE32 ®<br />
PowerTools<br />
Lauterbach offers the world’s most<br />
advanced and complete debug<br />
environment. With more than 30<br />
years of experience, Lauterbach’s<br />
TRACE32 ® product line has<br />
accumulated an arsenal of analysis<br />
tools suitable for most debug and<br />
testing requirements. These tools<br />
range from traditional source code<br />
debug to statistical analysis, code<br />
coverage, charting and profiling of<br />
your code execution.<br />
With much experience supporting<br />
the various ARM ® core architectures,<br />
including ARM Cortex-A, ARM<br />
Cortex-R, ARM Cortex-M,<br />
and other Coresight components,<br />
Lauterbach is proud to announce<br />
support for the latest ARM<br />
Cortex-M4/Cortex-A5 based<br />
<strong>Freescale</strong> Vybrid devices. Offering a<br />
4-bit ETM trace port, the Vybrid part<br />
unleashes many of the advanced<br />
analysis features offered by the<br />
Lauterbach TRACE32 debugger, at<br />
a reasonable price point. There are<br />
several levels of debugger support, with<br />
or without support for the ETM trace.<br />
TRACE32 ® Debugger<br />
for ARM Cortex-M or<br />
ARM Cortex-A/R<br />
The tools for the ARM Cortex-M/<br />
Cortex-A/R processor family<br />
are designed as an open debug<br />
environment that offers sophisticated<br />
features for quick and effective testing<br />
of your embedded design. It now<br />
supports the latest <strong>Freescale</strong> Vybrid<br />
devices with the ARM Cortex-M4/<br />
Cortex-A5 core.<br />
62<br />
TRACE32 Debugger<br />
Hardware Configuration<br />
The PowerDebug for the ARM<br />
Cortex-M processor family consists of:<br />
• A high-speed debug hardware<br />
module<br />
• A debug cable for the ARM Cortex-M<br />
or ARM Cortex-A/R devices<br />
A USB2.0 or Ethernet interface<br />
is provided as host interface to<br />
PC Windows, PC Linux ® or any<br />
workstation.<br />
Back to Table of Contents<br />
TRACE32 ® Debugger for ARM Cortex-M or ARM Cortex-A/R<br />
JTAG Debugger Features<br />
• Supports JTAG, SWD and cJTAG<br />
• C and C++ support for all standard<br />
compilers<br />
• Full and intuitive support of the<br />
on-chip debug unit<br />
• RTOS awareness for all commonly<br />
available RTOS<br />
• Real-time memory access via DAP<br />
• Flash programming support<br />
• Multicore debugging
Back to Table of Contents<br />
TRACE32 CombiProbe<br />
for ARM Cortex-M<br />
TRACE32 JTAG debuggers can<br />
be extended with the CombiProbe<br />
which adds 4-bit ETM real time trace<br />
capabilities to the debugger, enabling<br />
the industry’s finest code analysis and<br />
profiling tools.<br />
CombiProbe Hardware<br />
Configuration<br />
The CombiProbe PowerDebug for<br />
ARM Cortex-M processor family<br />
consists of:<br />
• High-speed debug hardware<br />
module<br />
• CombiProbe debug cable for<br />
recording the 4-bit ETM v3.x in<br />
continuous mode<br />
• License for ARM Cortex-M<br />
debugging<br />
A USB2.0 or Ethernet interface is<br />
provided as host interface to PC<br />
Windows, PC Linux or any work<br />
station. The product also includes<br />
CoreSight Single Wire Viewer.<br />
CombiProbe Features<br />
• Up to 128 MB trace entries<br />
• Trace port rates up to 200 Mbps<br />
• Real-time profiling<br />
• Long-time trace<br />
• Energy profiling<br />
• Re-debugging of all sampled<br />
program steps (CTS)<br />
• Trace filter and trigger<br />
• Run time analysis of functions and<br />
tasks<br />
• Code coverage and variable analysis<br />
• Multicore debugging<br />
TRACE32 PowerTrace<br />
for ARM Cortex-A/R or<br />
ARM Cortex-M<br />
TRACE32 JTAG debuggers can be<br />
extended with the PowerTrace which<br />
adds 4/8/16/32-bit ETM real-time<br />
trace capabilities to the debugger,<br />
enabling the industry’s finest code<br />
freescale.com/Vybrid<br />
analysis and profiling tools.This<br />
configuration supports all modes of<br />
the ETM trace port.<br />
PowerTrace Hardware<br />
Configuration<br />
The PowerTrace for ARM Cortex-M<br />
processor family consists of:<br />
• High-speed debug hardware<br />
module<br />
• PowerTrace module for recording<br />
4/8/16/32-bit ETM real-time trace<br />
• Debug cable for Cortex-A/R or<br />
Cortex-M debugging<br />
A USB2.0 or Ethernet interface is<br />
provided as host interface to PC<br />
Windows, PC Linux or any workstation.<br />
PowerTrace Features<br />
• Up to 4 GB trace entries (also,<br />
streaming to host for recording<br />
longer run times)<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
TRACE32 ® CombiProbe for ARM Cortex-M<br />
TRACE32 ® PowerTrace for ARM Cortex-A/R or ARM Cortex-M<br />
• Trace port rates up to 600 MHz at<br />
4/8/16/32-bit trace widths<br />
• Real-time profiling<br />
• Long-time trace<br />
• Energy profiling<br />
• Re-debugging of all sampled<br />
program steps (CTS)<br />
• Trace filter and trigger<br />
• Run time analysis of functions and<br />
tasks<br />
• Code coverage and variable analysis<br />
• Multicore debugging<br />
For more information about TRACE32<br />
tools, visit lauterbach.com.<br />
63
For more information, visit freescale.com/Vybrid<br />
<strong>Freescale</strong>, the <strong>Freescale</strong> logo, CodeWarrior, ColdFire, Kinetis, PowerQUICC and Qorivva are trademarks of<br />
<strong>Freescale</strong> <strong>Semiconductor</strong>, Inc., Reg. U.S. Pat. & Tm. Off. Processor Expert, Vybrid and Xtrinsic are trademarks<br />
of <strong>Freescale</strong> <strong>Semiconductor</strong>, Inc. ARM is the registered trademark of ARM Limited. ARM9, ARM11, ARM Cortex-A5,<br />
ARM Cortex-A9, ARM Cortex-M3 and ARM Cortex-M4 are trademarks of ARM Limited. Java and all other Java-based<br />
marks are trademarks or registered trademarks of Sun Microsystems, Inc. in the U.S. and other countries. The Power<br />
Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and<br />
service marks licensed by Power.org. All other product or service names are the property of their respective owners.<br />
© 2012 <strong>Freescale</strong> <strong>Semiconductor</strong>, Inc.<br />
Document Number: VYBRIDBYNDBITS REV 0