Beyond Bits VII - Freescale Semiconductor
Beyond Bits VII - Freescale Semiconductor
Beyond Bits VII - Freescale Semiconductor
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Memory Subsystem<br />
Flexible memory hierarchy for optimal code footprint,<br />
security and BOM cost<br />
Vybrid devices have multiple memory<br />
interface options. In addition to<br />
having up to 1.5 MB of on-chip<br />
SRAM for speedy code execution,<br />
Vybrid devices can interface to a<br />
variety of external peripherals and<br />
memories for system expansion<br />
and data storage. Dual Quad SPI<br />
interfaces with Execute-in-Place (XiP)<br />
support can interface with the latest<br />
flash memory. A secure digital host<br />
controller supports SD, SDIO, MMC<br />
or CE-ATA cards for in-application<br />
software upgrades as well as media<br />
files or adding Wi-Fi ® support. NAND<br />
flash and DRAM controllers with ECC<br />
support allow connection to a wide<br />
variety of memory types for critical<br />
applications. Battery-backed RAM is<br />
critical for secure systems to store<br />
authentication keys. Vybrid devices<br />
provide 16 KB of secure RAM and the<br />
platform provides 96 KB ROM for high<br />
assurance boot.<br />
The “Vybrid Memory Hierarchy”<br />
diagram illustrates the memory<br />
hierarchy of Vybrid devices and the<br />
various memory interfaces.<br />
freescale.com/Vybrid<br />
Tag 7<br />
(Optional)<br />
Vybrid Memory Hierarchy<br />
Tag 6<br />
0<br />
0<br />
Data<br />
7<br />
ARM ® Cortex-A5 Core Complex<br />
ITM + ETM + ETB + CTI<br />
FPU + NEON<br />
Inst<br />
Alu/ Q<br />
Mul Ld/Sc Shift<br />
Data uTLB<br />
STB<br />
D-$<br />
4 x 8K<br />
AXI System Bus<br />
TLB<br />
AXI-BIU<br />
PFU & Branch<br />
Predictor<br />
Inst uTLB<br />
L2 Cache Controller<br />
Vybrid DRAM Controller<br />
I-$<br />
2 x 16K<br />
NIC-301<br />
SDIO x2 NAND Flash DDRC Quad SPI x2 OCRAM<br />
_sys<br />
Network<br />
Inter-Connect<br />
(NIC)<br />
64-bit AXI<br />
64-bit AXI<br />
<strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition<br />
64<br />
64<br />
Multi-Port<br />
Arbitration<br />
Arbitration<br />
Engine<br />
OCRAM<br />
_sys<br />
OCRAM<br />
_gfx<br />
TPIU<br />
DAP<br />
DRAM Memory Controller<br />
Command<br />
Queue<br />
Ordering<br />
Engine<br />
Write<br />
Queue<br />
Read<br />
Queue<br />
Transaction<br />
Processing<br />
Sequence<br />
Engine<br />
Performance<br />
and Power<br />
Tuning<br />
Registers<br />
RAM<br />
Array, 32k<br />
Tag/Data<br />
Arrays, 2x 8k<br />
ARM ® Cortex-M4<br />
Core Complex<br />
NVIC<br />
FPU<br />
CM4 CPU<br />
FPB<br />
DWT CTI<br />
AP Bus Matrix ITM<br />
System Bus Code Bus<br />
TCMU<br />
Sys-$<br />
Sys BIU Code BIU<br />
TCML<br />
Code-$<br />
RAM<br />
Array, 32k<br />
Tag/Data<br />
Arrays, 2x 8k<br />
64 64 64<br />
AHB System Bus AHB Code Bus AHB Backdoor Port<br />
Boot<br />
ROMx2<br />
DFI Interface DFI Interface<br />
FlexBus PBRIDGE<br />
PHY<br />
Interface<br />
DLL<br />
ECC<br />
Device<br />
Interfaces<br />
DRAM<br />
DDR3<br />
LPDDR2<br />
35
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