Beyond Bits VII - Freescale Semiconductor

Vybrid Family Back to Table of Contents
Vybrid VF4xx Family
Single core solution with dual USB and integrated PHY
for mobility and automation
The VF4xx family features
the ARM ® Cortex-A5 core
with speeds up to 500 MHz
with 512 KB L2 cache, dual
USB 2.0 OTG controllers
with integrated PHY, 1 MB
of on-chip SRAM and a rich
suite of communication,
connectivity and humanmachine
interfaces (HMI).
Target Applications
• Building automation
• Gaming controllers
• Point-of-sale
Mixed-Signal Capability
• Two 12-bit ADCs with configurable
resolution. Single or differential
output mode operation for
improved noise rejection. 500
ns conversion time achievable
with programmable delay block
triggering
• Two 12-bit DACs for analog
waveform generation for audio
applications or sensor manipulation
Memory
• Dual Quad SPI supporting a double
data rate interface, an enhanced
read data buffering scheme,
Execute-in-Place and support for
dual-die flashes
• Boot ROM with optional high
assurance boot for secure booting
capability
• Up to 1 MB on-chip SRAM with
ECC support on 512 KB
10
Vybrid VF4xx Family
Faraday F400 Block Diagram
Debug and Trace
JTAG
Trace
Timers
FlexTimer (8-ch.)
FlexTimer (2-ch.)
FlexTimer (2-ch.)
FlexTimer (8-ch.)
IEEE ® 1588 Timers
Periodic Interrupt Timers
Low Power Timers
Memory
Boot ROM
1 MB SRAM
Memory Interfaces
DDR Controller
NAND Flash Controller
Quad SPI x2
External Bus Interface
• 16-bit DDR controller with PHY
and ECC support capable of
DDR3/LPDDR2 800 MHz data rate
Performance
System
AMBA NIC
Internal and
External Watchdog
Interrupt
Router
DMA
Up to 64-ch.
Power Management
Regulators
Memory Protection
Unit
TFT LCD
Touch Screen Controller
Video
Video Interface w/Camera
Audio
• ARM Cortex-A5 core with
frequency up to 500 MHz, with
double precision floating point,
NEON media processing engine
for acceleration of media and
signal processing, and TrustZone
security extension. 32 KB each of
instruction and data L1 cache and
512 KB L2 cache for optimized
bus bandwidth and on-chip SRAM
execution performance
• Up to 64-channel DMA for
peripheral and memory servicing
with reduced CPU loading and
faster system throughput
ARM ® Cortex-A5
Up to 500 MHz
• Crossbar switch enables
concurrent multi-master bus
accesses, increasing bus
bandwidth
Timing and Control
• Four flex timers with a total of 20
channels. Hardware dead-time
insertion and quadrature decoding
for motor control
• Four-channel 32-bit periodic
interrupt timer provides time base
for RTOS task scheduler or trigger
source for ADC conversion and
programmable delay block
HMI
Core
DP-FPU
NEON
L1 I/D-Cache
L2 Cache
Trace/Debug
GIC
Display Security
ASRC
SAI x4
ESAI
Crypytography Module
Tamper Detect
Secure RTC
Secure RTIC
Secure RAM
Secure Fuses
Secure WDOG
Secure JTAG
Analog
12-bit ADC x2
12-bit DAC x2
PLL
Clocks
Clock
Monitors
Internal Reference
Clocks
Low/High Frequency
Oscillators
Communication
UART x6 CAN x2
DSPI x4 I 2 C x4
IEEE 1588
Ethernet
USB Host + PHY
LS/FS/HS
USB OTG + PHY
LS/FS/HS
Secure Digital x2
141 GPIO
(with Interrupt)
• TFT LCD display capable of up to
XGA resolution