Beyond Bits VII - Freescale Semiconductor

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Technical Highlights FlexBus The FlexBus interface on the Vybrid devices is designed to gluelessly connect with up to six external devices. Each version has 8-, 16- and 32-bit port sizes with configuration for multiplexed or non-multiplexed addresses and data buses. Features • Byte-, halfword-, word- and 16-byte line-sized burst transfers • Programmable burst and burst inhibited transfers selectable for each chip select and transfer direction • Auto-acknowledge feature Primary wait state counter up to 63 clocks Optional secondary wait state counter Useful for interfacing to burst memories that have a long access time for the first beat of data, but can deliver subsequent data faster • Programmable address setup time with respect to the assertion of chip select • Programmable address hold time with respect to the negation of chip select and transfer direction Flexbus supports the connection to: • Flash • Smart LCDs • FPGAs • SRAM • PROM • EPROM • EEPROM 38 FlexBus Modes of Operation of Operation Non Muxed Mode FlexBus Key Features Customer Benefits Back to Table of Contents 8-, 16-, 32- and 128-bit line sized transfers Maximize throughput according to the specific application Programmable burst and burst-inhibited transfers selectable for each chip select and transfer direction Optimized traffic patterns for each client in the bus Auto-acknowledge feature Increased flexibility and lower BOM costs in glueless external device connections Programmable address-setup time Programmable address-hold time Data Data Data Data Address Address Address Address Data and Address Have Separate Ports Muxed Mode Address Data Data Address Data and Address Are Interleaved on the Same Port Smart LCD Mode Data Data Data Data Data Is Sent Sequentially on One Port
Back to Table of Contents The universal asynchronous receiver/ transmitter (UART) module in Vybrid devices allows for asynchronous, full-duplex serial communication in a variety of formats. Features of the UART include: • Standard mark/space non-return-tozero format • Supports IrDA 1.4 return-to-zeroinverted format • Supports ISO 7816 protocol for interfacing with SIM cards and smartcards (feature supported on one UART module only) • 13-bit baud rate selection with by-32 fractional divide • Programmable eight- or nine-bit data formats • Ability to select MSB or LSB to be first on the wire • Hardware flow control support for request to send and clear to send signals • Separate transmit and receive (feature supported on two UART modules only) FIFOs with DMA request capability ISO 7816 Support Two of the UART modules support the ISO 7816 standard, allowing communication with SIM cards and smartcards. This feature has the following characteristics: • Supports T=0 and T=1 protocols • Automatic retransmission of NACKed packets with programmable retry threshold • Supports 11 and 12 ETU transfers • Detects initial packet and automated transfer parameter programming freescale.com/Vybrid UART Transmit Logic UART Transmit Logic Module Clock ISO ISO 7816 7816 Timing Timing Diagrams Diagrams ISO 7816 Format without Parity Error (T=0) START BIT BIT 0 BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITY BIT STOP BIT STOP BIT ISO 7816 Format with Parity Error (T=0) START BIT BIT 0 ISO 7816 Format (T=1) START BIT Baud Rate Generator SBR12:0 BRFA4:0 PE PT BIT 0 M10 M TXINV MSBF Parity Generation <strong>Beyond</strong> <strong>Bits</strong> Vybrid Edition Universal Asynchronous Receiver/ Transmitter A flexible approach to full-duplex serial communication Stop IRQ/DMA Logic Internal Bus SCI Data Register (SCID) Variable 12-bit Transmit Shift Register Shift Direction 7816 Logic Infrared Logic Start Transmitter Control TXDIR SBK TE BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITY BIT BIT 1 BIT 2 BIT 3 BIT 4 BIT 5 BIT 6 BIT 7 PARITY BIT R485 Contol Loop Control To Receiver NACK ERROR STOP BIT TXD Pin Control Tx port en Tx output buffer en Tx input buffer en DMA Done TxD NEXT START BIT TxD DMA Requests IRQ Requests LOOPS RSRC RTS_B CTS_B NEXT START BIT STOP BIT NEXT START BIT 39
Page 1: BeyondBits Issue 7 VYBRID EDITION R
Page 4 and 5: Vybrid Family Overview 4 Vybrid Con
Page 6 and 7: Vybrid Controller Solutions Vybrid
Page 8 and 9: Vybrid Family Back to Table of Cont
Page 20 and 21: Technical Highlights
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Page 24 and 25: Technical Highlights Multicore Comm
Page 26 and 27: Technical Highlights Multimedia Sub
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Page 30 and 31: Technical Highlights platform. HAB
Page 32 and 33: Technical Highlights Power Domains
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Page 36 and 37: Technical Highlights Features • C
Page 38 and 39: Technical Highlights Vybrid DRAM Co
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Beyond Bits VII - Freescale Semiconductor

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