Beyond Bits VII - Freescale Semiconductor

Technical Highlights
FlexBus
The FlexBus interface on the Vybrid
devices is designed to gluelessly
connect with up to six external
devices. Each version has 8-, 16- and
32-bit port sizes with configuration
for multiplexed or non-multiplexed
addresses and data buses.
Features
• Byte-, halfword-, word- and 16-byte
line-sized burst transfers
• Programmable burst and burst
inhibited transfers selectable for
each chip select and transfer
direction
• Auto-acknowledge feature
Primary wait state counter up to
63 clocks
Optional secondary wait state
counter
Useful for interfacing to burst
memories that have a long
access time for the first beat of
data, but can deliver subsequent
data faster
• Programmable address setup time
with respect to the assertion of chip
select
• Programmable address hold time
with respect to the negation of chip
select and transfer direction
Flexbus supports the connection to:
• Flash
• Smart LCDs
• FPGAs
• SRAM
• PROM
• EPROM
• EEPROM
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FlexBus Modes of Operation of Operation
Non Muxed Mode
FlexBus Key Features Customer Benefits
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8-, 16-, 32- and 128-bit line sized transfers Maximize throughput according to the specific
application
Programmable burst and burst-inhibited transfers
selectable for each chip select and transfer
direction
Optimized traffic patterns for each client in
the bus
Auto-acknowledge feature Increased flexibility and lower BOM costs in
glueless external device connections
Programmable address-setup time
Programmable address-hold time
Data Data Data Data
Address Address Address Address
Data and Address Have Separate Ports
Muxed Mode
Address Data Data Address
Data and Address Are Interleaved on the Same Port
Smart LCD Mode
Data Data Data Data
Data Is Sent Sequentially on One Port