1A -CSOL3, U211-9B QO, U211-2V:H:2V/dlv50 us/divWaveform 2-2POT MUX LATCHU211's state is undetermined on power-up, since the computer has not yet had time to initialize the POTMUX by setting aii inhibits high. U211 might well "come up" with more than one low for Q2, Q3, andQ4. In such cases two or more pots would be connected together at Vmux. The current surge resultingfrom any significant potential difference between their settings would instantly destroy a 4051, were itnot for R203/R206/R209.To check the pots the CPU first places data 18H on the bus and clocks the POT MUX address latch with-CSOL3. This sets Q2 and Q4, inhibiting U201 and U202. With Q3 reset (0),U203 connects R105 FILT ATKwiper from pin 13 to 3. If the knob is set halfway, +2.5V (Vmux) will appear at the common input of theADC CPR, U365-9/10 (see schematic SD332).Next the CPU takes the first pot table byte from SPAD RAM, places it on the bus, and latches it to theDAC HI latch U337 (and U342-5), port -CSOH7. If we assume this pot has not changed position since the'ast loop, the converted data should compare with Vmux. Thus data 3C(H) pulls DAC bits 11, 12, 13, and14 low through U344/45 inverters. The DAC has a current output which U347 converts to voltage, in thiscase 5V (2.667 + 1.333 + 0.666 + 0.333V). R334/35 and R336 divide by two so 2.5V appears at U364-7. Sincethis equals Vmux, neither comparator output goes high. The network containing D306/07, and R366-71provide ''hysterisis", such that the difference between Vdac/2 and Vmux must be more than 34 mVbefore the comparator will activate. Pot drift is also eliminated through software hysterisis whichwatches the direction of pot changes. A pot must move two steps in the same direction to qualify as alegitimate change. To check the remaining pots, the CPU latches data 19-1F, 28-2F, and 30-37(H) to port-CSOL3. When done, data 38(H) clears the POT MUX. Waveform 2-3 details Vmux.Having updated its Scratchpad RAM tables of switch and key status and of pot values, the CPU is nowready to output the appropriate CVs. Certain adjustments need to be performed, such as figuring thetuning biases according to the notes to be sounded (see paragraph 2-13), and inverting the envelopegenerator timing voltages (see paragraph 2-7). If UNISON mode is on, the KBD CVs are removed fromthe OSC S/Hs. GLIDE CV is also switched on in UNISON2-17
iirH- - jMg 1— -^ 'iVMUX, U201-3^^4liM'p ^-.-^.^^S ^ .^i-j y^ V .. V ^ -p ^ -J "t y' ^ ^.^ >1 - .p, ^Vy^ ^ ^y^ - V J^V>
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- Page 3 and 4: PROPHET-5 SYNTHESIZERTECHNICAL MANU
- Page 5 and 6: iJTable of ContentsISECTION 1MECHAN
- Page 7 and 8: '1SECTION 1MECHANICAL1-0 GENERALThi
- Page 9 and 10: Raise the top panel assembly to ser
- Page 11 and 12: 1-5 PCB 1/2 CONTROL PANELSOnce PCB
- Page 13 and 14: Figure 1-5KEYBOARD REMOVAL1 -7/1 -8
- Page 15 and 16: TOADDITIONALVCOsTOADDITIONALENV GEN
- Page 17 and 18: 2-2 THE PROPHETThe Prophet is a sub
- Page 19 and 20: COMMON ANALOGVOICE(VOiCES e-5 ARE S
- Page 21 and 22: 'IAll processed CVs originate from
- Page 23 and 24: ajMim—2-8 AUDIO OUTPUTAs shown in
- Page 25 and 26: .'2-10 MICROPROCESSOR, MEMORY, AND
- Page 27 and 28: For troubleshooting, it should be e
- Page 29: 2-12 ADC, DAC, AND CV OUTPUTSThe DA
- Page 33 and 34: the same CV and trigger pattern to
- Page 35 and 36: SECTION 3DOCUMENTS3-0 DOCUMENT LIST
- Page 37 and 38: TOP PANEL ASSEMBLY1CHASSiSLAST \NOT
- Page 39 and 40: TB/0i/20f 32 22 30 20 19 25 233 2 I
- Page 41 and 42: TBZOf/^fOtP^2C20ZTBZOI/IOl17FUT ATK
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- Page 47 and 48: 1+ I5V£/JJiJ-5|T> -TUNEWBOtWfOiAMP
- Page 50 and 51: P40I+I6V(TUNE MUX)P40iP40f3ft wMIK
- Page 52 and 53: + I5VOSCP40i^Q ^ |PMOPFR£QASFINAL
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- Page 56 and 57: IU504ft50647C5042Z00|iFMCTBMtZCT2 1
- Page 58 and 59: Inpreparation for service, set up t
- Page 60 and 61: 4-2 OSCILLATOR B TESTSTEP MODULE CO
- Page 62 and 63: 4-S FILTER TEST.STEP'MODULE CONTROL
- Page 64 and 65: 4-8 POLY-MOD TEST—A.STEP MODULE C
- Page 66 and 67: i4-11 PITCH WHEEL TRIMThis trim rem
- Page 68 and 69: A)I4-16 VCO SCALE TRIMBE SURE RECOR
- Page 70 and 71: 4-19 FILTER ENVELOPE AMOUNT VCA BAL
- Page 72 and 73: 4-21 FINAL VGA BAL1. Switch PRESET
- Page 74 and 75: 115-3 PCB 3BT301 E-040L-\:!Oi 0-U45
- Page 76 and 77: I ]U374U375U376U377U37SU379U380U381
- Page 78 and 79: 1R419SR4199R4200R4201R4202R4203R420
- Page 80 and 81:
51» IR44S7/488 R-025R44S9 R-009R44
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kL096 E-066098 E-071100 E-078102 E-
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IJ310 M-156312 M-157314 M-158316 M-
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JJ51S R-161520 R--162522 R-163524 R
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11 IJSECTION 8THEORY8-0 INTRODUCTIO
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1 1for the 2 to 5-foot range. The c
- Page 94 and 95:
IiSECTION 9PRCX^RAMMING9-0 INTRODUC
- Page 96 and 97:
I3JIJThe Prophet will not accept st
- Page 98 and 99:
ByteByte 23Switch Bit (7)OSC A PULS
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t J IISECTION 10REVISION 3.1 and 3.
- Page 102 and 103:
I+ I5V+5dI^1-+5V 2'2pF+I6V+5V^^' U3
- Page 104 and 105:
T&=* PANEL ASSE^^mtYSAfKEYBOARD,'r-
- Page 106 and 107:
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- Page 112 and 113:
^ 1 1 ;4 PINFigure II-OFigure11-TM1
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I 111-2 REVISION 3.0 MEMORY TESTRev
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Tr1 1-5 WHEEL BALANCE TRIM1. See pa
- Page 118 and 119:
SECTION 13PROPHET-5 REV 3.3 UPDATET
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iFigure 13-1PCB 3 TOP MODIFICATIONT
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- Page 128 and 129:
tV t IEPROM1000.3.0V.8.0V.8.1V.8.21
- Page 130 and 131:
IJmemory interface1000.3.01000.3.11
- Page 132 and 133:
ittKRAM, non-volatile (NV)1000.3.01
- Page 134:
1voltage-current convertervoice ass
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