1 1for the 2 to 5-foot range. The clock speed influences cable performance, since datatransfered at higher speeds encounters nnore reactance (hence, degradation) in thecable.USART OPERATIONNormally U386 USART stands unused. But it is initialized to interrupt the CPU whenserial data is received. When the CPU is interrupted, it stops whatever it is doing andreads the USART data as if it were reading a memory device. The CPU can also outputa byte to the USART. As discussed in the section on programming, this data exchangeenables sequencing and remote keyboard control.In more detail, pin 21 RESET connects to the CPU -RESET through inverter-wiredU382-3. When power comes on, RESET clears the USART's internal registers and sets itto Idle. To operate, it must be initialized with the appropriate bytes sent to its controlregisters.The USART connects to the Address Bus. AO and Ai select, while A 15 actuallyprograms the reading and writing to or from the USART's receive, transmit, or controlregisters.While the Address Bus is used to program the USART, its data lines remain tri-stateduntil pin 11 -CS goes low. The CPU sends commands and output data to the USART overthe Data Bus. The USART sends input data and its own status bytes (as opposed tostatus bytes sent by the external sequencer) to the CPU.After resetting and initializing the USART, it is set-up to respond to data input asfollows. Through the Low-Voltage Ouput Port Decoder U319, the CPU sets pin 10-CSOL5 low. On Rev 3.0 this signal cleared the monophonic sequencer Interface toGATE 5. On Rev 3.2 this signal clears the Interrupt Flip-Flop U330-2 (see SD352), whileGATE 5 is controlled separately. (GATE 5 is now memory-mapped. It is enabled byU318-10, through inverter U3^3-6 and Flip-Flop U330-13.)Once the Flip-Flop is reset, U330-2 -INT is high. Notice U385-8, the AND gate(converted to negative logic by DeMorgan) connected to USART pin U RxRDY. -INTconnects to U385-9. Pin 10 ispulled high by R3153. Thus, with both inputs high, U385-8--which actually connects to the CPU—is high and the CPU runs normally.The CPU is interrupted either by the USART signalling that it has received a byte, orby a GATE occuring through the monophonic sequencer interface. In the first case, theUSART RxRDY pin goes low when the USART has received a serial data byte.Whenever the -INT occurs, the CPU first examines the USART to see if its receivingregister is holding data. If not, then the -INT must have arisen from the monophonicsequencer interface.In this second case, the high SEQ GATE IN (J3) is inverted by U33U^, delayed slightly,and re-inverted by U331-2 to clock the Interrupt Flip-Flop U330-2. Since pin 5 D is tiedhigh, pin 1 Q goes high, and pin 2 -Q goes low, generating the -INT.TM1000D.2 10/81 8-3
1 J8-2 REVISION 3.2 ANALOG and POWER SUPPLY116 ANALOG INTERFACE connector is SCI //J-05^- To mate, use SL-40-5M, SCI //P-05^, The pin specifications are:WARNING! Since we have no idea what you will beIconnecting to these inputs, wecannot guarantee this interface will work with any custom device. You are completelyresponsible for any damage to the <strong>Prophet</strong> which may resultaccessories.Pin 1, GROUNDfrom connecting non-SCIPin 3, +22V, unregulated, 50 mAPin 5, -22V, unregulated, 50 mAThese two supplies have 5.1-ohm current-limiting resistors (see SD551). But accessoriesshould be fully tested with another power source before connecting to these supplies.WARNING! The <strong>Prophet</strong> can be damaged ifprotection of the <strong>Prophet</strong>, itthese supplies are tampered with. For bestis best to avoid using these supplies.Pin ^, PITCH WHEEL CONTROL VOLTAGE INPUT (P-WH CV IN)This input raises or lowers the pitch of all five voices. The voltage applied should benominally zero for the instrument to be tuned to A-4^0. Both positive and negativevoltages can be applied. The <strong>Prophet</strong> disables this input during its TUNE routine toprevent accidental detuning.Pin 2, MODULATION WHEEL CONTROL VOLTAGE INPUT (M-WHCV IN)This input ranges - +10V, with maximum modulation being applied at +10V. Do notapply a negative voltage to this input.Rev 3.2 changes to the Common Analog section are shown on SD35^. The MOD Wheelcircuitry has gained a Summer U374-8 to add the Mod Wheel CV and an external ModCV together. VGA U381-12 allows the remote voltage control, and introduces WHEELBAL trimmer R316S. Trim procedure is in Section 11.Remote PITCH CV input required switch U377-10 to disable this input during the TUNEroutine.8-^ TM1000D.2 10/81
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PROPHET-5 SYNTHESIZERTECHNICAL MANU
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iJTable of ContentsISECTION 1MECHAN
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'1SECTION 1MECHANICAL1-0 GENERALThi
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Raise the top panel assembly to ser
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1-5 PCB 1/2 CONTROL PANELSOnce PCB
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Figure 1-5KEYBOARD REMOVAL1 -7/1 -8
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TOADDITIONALVCOsTOADDITIONALENV GEN
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2-2 THE PROPHETThe Prophet is a sub
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COMMON ANALOGVOICE(VOiCES e-5 ARE S
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'IAll processed CVs originate from
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ajMim—2-8 AUDIO OUTPUTAs shown in
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.'2-10 MICROPROCESSOR, MEMORY, AND
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For troubleshooting, it should be e
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2-12 ADC, DAC, AND CV OUTPUTSThe DA
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iirH- - jMg 1— -^ 'iVMUX, U201-3^
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the same CV and trigger pattern to
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SECTION 3DOCUMENTS3-0 DOCUMENT LIST
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TOP PANEL ASSEMBLY1CHASSiSLAST \NOT
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TB/0i/20f 32 22 30 20 19 25 233 2 I
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- Page 45 and 46: —' i+6V+5d^1—+I5V+ SV+ V ff^ U3
- Page 47 and 48: 1+ I5V£/JJiJ-5|T> -TUNEWBOtWfOiAMP
- Page 50 and 51: P40I+I6V(TUNE MUX)P40iP40f3ft wMIK
- Page 52 and 53: + I5VOSCP40i^Q ^ |PMOPFR£QASFINAL
- Page 54 and 55: M+I5VP40/ x|5v301 K|%34^fM0O£WASR4
- Page 56 and 57: IU504ft50647C5042Z00|iFMCTBMtZCT2 1
- Page 58 and 59: Inpreparation for service, set up t
- Page 60 and 61: 4-2 OSCILLATOR B TESTSTEP MODULE CO
- Page 62 and 63: 4-S FILTER TEST.STEP'MODULE CONTROL
- Page 64 and 65: 4-8 POLY-MOD TEST—A.STEP MODULE C
- Page 66 and 67: i4-11 PITCH WHEEL TRIMThis trim rem
- Page 68 and 69: A)I4-16 VCO SCALE TRIMBE SURE RECOR
- Page 70 and 71: 4-19 FILTER ENVELOPE AMOUNT VCA BAL
- Page 72 and 73: 4-21 FINAL VGA BAL1. Switch PRESET
- Page 74 and 75: 115-3 PCB 3BT301 E-040L-\:!Oi 0-U45
- Page 76 and 77: I ]U374U375U376U377U37SU379U380U381
- Page 78 and 79: 1R419SR4199R4200R4201R4202R4203R420
- Page 80 and 81: 51» IR44S7/488 R-025R44S9 R-009R44
- Page 82 and 83: kL096 E-066098 E-071100 E-078102 E-
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- Page 86 and 87: JJ51S R-161520 R--162522 R-163524 R
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- Page 98 and 99: ByteByte 23Switch Bit (7)OSC A PULS
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