LECTURE 040 Ã¢Â€Â“DIGITAL PHASE LOCK LOOPS (DPLLs)

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Lecture 040 – Digital Phase Lock Loops (DPLLs) (09/01/03) Page 040-23The Pull-In Range, ∆ω p , and the Pull-In Time, T pThe pull-in range, ∆ω p , is the largest ∆ω = |ω 1 −ω 2 ’| for which an unlocked loop will lock.The pull-in time, T p , is the time required for the loop to lock.EXOR as the PD:Waveformsvd0.5K d π-0.5K d πT 1 T 2T = 2π/∆ωttFig. 2.2-28CMOS Phase Locked Loops © P.E. Allen - 2003ω 2 '∆ω(t)ω oT = 2π/∆ωT 1 > T 2 because ∆ω is smaller when v d is positive and larger when v d is negative.Results-Type of Filter ∆ω p (Low loop gains) ∆ω p (High loop gains) Pull-in Time, T pPassive Lagπ2 2ζω πnK o K d - ω 2 n2 ζω nK o K4 o 2dπ 2 ζω 3 nActive Lag π2 2ζω n K o K d - ω n 2 πK a2 ζω nK o K4 o 2dπ 2 ζω 3 nActive PI ∞ ∞ 4 o 2π 2 ζω 3 nω 1ω 2 'Lecture 040 – Digital Phase Lock Loops (DPLLs) (09/01/03) Page 040-24The Pull-In Range, ∆ω p , and the Pull-In Time, T p -ContinuedJK Flip-Flop as the PD:WaveformsvdK d π-K d πT 1 T 2T = 2π/∆ωtω 2 'ω o∆ω(t)T = 2π/∆ωω 1ω 2 'tFig. 2.2-29T 1 > T 2 because ∆ω is smaller when v d is positive and larger when v d is negative.Results-Type of Filter ∆ω p (Low loop gains) ∆ω p (High loop gains) Pull-in Time, T pPassive Lag π 2ζω n K o K d - ω 2 n π 2 ζω n K o K d 1 o 2π 2 ζω 2 nActive Lagπ 2ζω n K o K d - ω n 2 π 2 ζω n K o K d 1 ∆ω o 2K a π 2 ζω 2 nActive PI ∞ ∞ 4 ∆ω o 2π 2 ζω 2 nCMOS Phase Locked Loops © P.E. Allen - 2003
Lecture 040 – Digital Phase Lock Loops (DPLLs) (09/01/03) Page 040-25∆ω p and T p for the PFDAssume that the PFD uses a single power supply of V DD . The various waveforms are,v 1V DD0.5V DDv 2 'v d0 tv d (eq.)V DDv dHighImpedanceState0.5V DD(If the filter time constant >> the duty cycle, this waveform simplifies the analysis.)0 tv fV DD0.5V DDω 1∆ωKov d (eq.) is a 50% duty cycle model of the PFD to find T p .T PtFig. 2.2-30CMOS Phase Locked Loops © P.E. Allen - 2003Lecture 040 – Digital Phase Lock Loops (DPLLs) (09/01/03) Page 040-26∆ω p and T p for the PFD – ContinuedSince ∆ω p = ∞, let us find T p using the following model for the passive lag filter:+V R DD1 +R 2v2d C-PFDFilter100% Duty Cycle+v f-V DD2PFD+v d-R 1 +R 22CFilter+v f-50% Duty Cycle Fig. 2.2-31Use the 50% duty cycle model, solve for the time necessary to increase v f by ∆ω/K o .1.) Loop filter = Passive lag⎛ K⎜ o V DD /2 ⎞⎟T p = 2(τ 1 +τ 2 ) ln⎜⎟⎝K o V DD /2 - ∆ω o ⎠2.) Loop filter = Active lag⎛ K⎜ o K a V DD /2 ⎞⎟T p = 2τ 1 ln⎜⎟⎝K o K a V DD /2 - ∆ω o ⎠3.) Loop filter = Active PIT p = 2τ 1∆ω oK o V DD /2For split power supplies, replace V DD with (V OH -V OL ).CMOS Phase Locked Loops © P.E. Allen - 2003
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LECTURE 040 Ã¢Â€Â“DIGITAL PHASE LOCK LOOPS (DPLLs)

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