LECTURE 040 –DIGITAL PHASE LOCK LOOPS (DPLLs)
LECTURE 040 –DIGITAL PHASE LOCK LOOPS (DPLLs)
LECTURE 040 –DIGITAL PHASE LOCK LOOPS (DPLLs)
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Lecture <strong>040</strong> – Digital Phase Lock Loops (<strong>DPLLs</strong>) (09/01/03) Page <strong>040</strong>-31NOISE PERFORMANCE OF THE DPLLCombination of Noise and InformationIn the LPLL, the noise and information signals are added because of the linearmultiplier PD.The noise supression of DPLL’s is generally better than LPLL’s but no theory of noiseexists for the DPLL.The following pages provide some insight into the noise performance of the DPLL.CMOS Phase Locked Loops © P.E. Allen - 2003Lecture <strong>040</strong> – Digital Phase Lock Loops (<strong>DPLLs</strong>) (09/01/03) Page <strong>040</strong>-32Noise Performance of a DPLL with an EXOR PDθ jv 1v 2 'v dPhase noise ata given inbandfrequencytInput withphase noisesuperimposed(phase jitter)v 1jθ j θ j θ jIdeal Inputθ j θ j θ jDetectorOuputv d100%50%0%v d is proportionalto the phase noise.∴ LPLL noise theory≈ DPLL noise theory.tFig. 2.2-32CMOS Phase Locked Loops © P.E. Allen - 2003
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