XPLA Designer v2.1 User's Manual

wide logic functions using 1 or up to 32 of the PLA product terms will add an additionaldelay (see individual data sheets for PLA delay time). Implementing wide logic functionsusing multiple passes through the logic array adds a Tpd delay for every additional logicarray pass. If speed is the most important parameter, the design should specify a largervalue for the “Maximum Product terms per Equation”. If fitting the design is perceived tobe an issue (density problem) and speed is not as important, then the user should specify asmaller value for the “Maximum Product Terms per Equation”.Activate D/T register synthesisThe Activate D/T register synthesis selection instructs XPLA Designer to minimize thenumber of product terms using either D or T Type flip-flops. When the selection isactivated, the software will implement each equation using all D or all T Type flip-flopsand it will pick the flip-flop type that requires the minimum number of product terms. Ifthe number of product terms are the same with either implementation, the XPLA Designerwill default to a D-Type flip-flop.If this selection is not activated, the XPLA Designer will use the type of flip-flop specifiedin the PHDL source code. If the register type is not specified in the PHDL source code,the XPLA Designer will default to a D-Type flip-flop.Auto Node Collapse ModeThe Auto Node Collapse Mode is used to minimize the number of passes through thelogic array by collapsing internal nodes into other logic. Collapsing the node frees amacrocell at the expense of using more PLA terms, thus maximizing design performancebecause one pass through the PAL and PLA arrays is faster than multiple passes throughthe PAL array. When the Auto Node Collapse Mode is used, the compiler will attempt tocollapse all internal nodes except those that have the keep attribute specified. When theAuto Node Collapse Mode is not used, the compiler will not attempt to collapse anyinternal nodes unless the collapse attribute has been specified.Fitter Option ExamplesThe following subsections give design examples of how the fitting options can be used tooptimize the design to meet the user’s individual needs.Constraining Pins and Nodes ExampleOne of the features of Philips CPLDs is that you can route virtually 100% of all designswith all pins locked, and all of the macrocells and pins used. This ensures that you can101