XPLA Designer v2.1 User's Manual

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Input PinTpd_pal = Combinatorial PALonlyTpd_pla = Combinatorial PAL + PLAOutput PinInput PinRegisteredTsu_pal = PAL onlyTsu_pla = PAL + PLADQRegisteredTcoOutput PinclockFigure 7Closing RemarksThe XPLA TM architecture used in the Philips CoolRunner CPLD family combines a uniquepower saving design technique with a next generation architecture. For any questionsconcerning the architecture, please contact Philips Programmable Products technicalsupport via the contact information detailed in Chapter 1.20
Chapter 4Getting Started with XPLA DesignerThis chapter provides a tutorial which demonstrates how to create, compile, and simulatea design using XPLA Designer. The design uses the Philips Hardware DescriptionLanguage to define a state machine.Design DescriptionThis getting started chapter targets a design called T-Bird Tail Lights into a PhilipsPZ3032 CPLD. This design is a state machine that simulates the blinkers and tail lights onFord Thunderbird automobiles of the late 1960s (see Figure 8). The inputs to the statemachine are clock (CLK), turn left (TL ), turn right (TR), and brake. The outputs of thedesign are the left blinkers (L1, L2, and L3) and the right blinkers (R1, R2, and R3). Whenturning left or right, the blinkers sequence through three bulbs to indicate the direction ofturn (see Figure 8). Starting with the inside bulb, three bulbs are sequentially lighted inthe direction of the turn until all three are on; then all three go dark and the sequencestarts again. When only the brake is applied, all six bulbs will light. If the brake and a turnsignal are applied simultaneously, the turn signals function as above, but all three lights onthe side opposite the direction of turn will light.CALIFORNIAPZ5032CALIFORNIAPZ5032CALIFORNIAPZ5032CALIFORNIAPZ5032Figure 8To begin, from the Windows Program Manager double-click on the XPLA Designer iconto invoke the tool. The XPLA Designer (Figure 9) user-interface consists of a menu bar atthe top, design entry options on the left hand side, compilation options on the right handside, and program execution options (compile, simulate, fit) at the bottom. Contextsensitive help for the design entry and compilation option sections is provided just belowthe respective sections. Move the cursor over the fixed menus and read the context21
Page 1 and 2: XPLA Designer
Page 3 and 4: XPLA Designer version 2.1 User’s
Page 5 and 6: SCL Brief .........................
Page 7 and 8: ARITHMETIC CIRCUIT: 4 X 4 MULTIPLIE
Page 9 and 10: the user through this design proces
Page 11 and 12: Device FittingDevice fitting is whe
Page 13 and 14: Chapter 2 Installing XPLA DesignerS
Page 15 and 16: Chapter 3XPLA TM Architecture Overv
Page 17 and 18: The XPLA TM architecture is very ac
Page 19: 5ProgrammableANDArray55...Figure 6S
Page 23 and 24: New design filenames must use a .ph
Page 25 and 26: the CPLD utilization and pinout. Th
Page 27 and 28: more information. The simulator is
Page 29 and 30: defined without returning to the Ch
Page 31 and 32: Using the ProgrammerIf a programmer
Page 33 and 34: Reserved WordsThe following keyword
Page 35 and 36: Order of OperationsFigure 21 define
Page 37 and 38: Header SectionThe header section of
Page 39 and 40: The header of all PHDL files must s
Page 41 and 42: Module macrotstTitle 'Using macro t
Page 43 and 44: dirloadcount_enabclkpin;pin;pin;pin
Page 45 and 46: "Declare the outputscount_out = [p1
Page 47 and 48: is illegal because buried1 cannot b
Page 49 and 50: "Create a variable for counter outp
Page 51 and 52: MODULE adderTITLE ‘Two four bit a
Page 53 and 54: n1 = q3.q & q2.q;count.ar = rst # n
Page 55 and 56: dir pin;c15..c0pin istype 'reg';"De
Page 57 and 58: in them directing the state diagram
Page 59 and 60: 5055606570758085state s2:when (BRAK
Page 61 and 62: [input state 3] :> [output state 3]
Page 63 and 64: if (TL ) then s3else if (TR) then s
Page 65 and 66: The simulator utilizes five logic l
Page 67 and 68: Figure 33Description of Simulator m
Page 69 and 70: This command allows the operator to
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Figure 37Del SignalThis command wil
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Add BusThis command will allow the
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Figure 43Set ValueThis command allo
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Figure 45Figure 4677
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Figure 4879
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Figure 50Transition CheckThis comma
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Figure 52To measure the difference
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• Events [+, -]• Create [Bus, C
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Figure 61Press the Create Bus butto
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Figure 68• Practice Design Simula
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Figure 74The Demo design comes with
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Figure 76Now click on the run butto
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Statements that handle signals, dat
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DescriptionFormatPT Print Title PT
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Chapter 7 Controlling the Fitting P
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wide logic functions using 1 or up
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MODULE count_16TITLE '16-bit Loadab
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Figure 88As one can see from Figure
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that may be summed for any macrocel
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Chapter 8PHDL Language ReferenceThe
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a,b,c,doutpin;pin istype 'com,inver
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when (in1 == 1) & (in2 == 1) then o
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equationsDescriptionThe reserved wo
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state [1,1]: goto [0,0];endif-then-
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Multiple if-then-else structureModu
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endistypeDescriptionThe istype stat
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macroDescriptionThe reserved word m
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signal_namenode istype ‘attribute
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XPLA property 'dut on';inoutpin;pin
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State indicates the state that is b
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state [0,1]: out = 1;if (in1 == 1)
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Module whenthenTitle 'Example of si
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out1.c = clk;out2.c = clk;when (in1
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out.c = clk;s1.c = clk;state_diagra
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Figure 92 shows the simulation mode
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* Simple SCL file (any comment is O
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Data Fields1. A data field consists
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3-State (pull-up or pull-down) resi
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This process is repeated until all
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FFinishFormatFThe Finish command te
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IFVCondition Check on a VariableFor
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Example:||SU TIME = 10000LIST UNDEF
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This command is used to reinitializ
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B set to 1C set to 0D set to 1* Now
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SU TIME = *+500Assuming an actual t
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Appendix BDevice Pin Out Configurat
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PZ3064/PZ5064 44 Pin PLCCPin Name N
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PZ3064/PZ5064 68 Pin PLCCPin Name N
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PZ3064/PZ5064 100 Pin PQFPPIN NAME
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Page 171 and 172:
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8-Bit Shift RegisterModule _8bshift
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8-Bit Adder - High LevelMODULE adde
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4-Bit Adder with Carry in and Carry
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Bidirectional I/O’sMODULE bidirec
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16-Bit Counter - Low Levelmodule cn
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}}else{}else when (dir == 1) then{c
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16-Bit Gray Code Countermodule gcnt
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& !q5 & !q4 & !q3 & !q2 & !q1 & !q0
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& q5 & !q4 & !q3 & !q2 & !q1 & !q0
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4-Bit Gray Code Countermodule gray4
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Timer/Countermodule p2" Timer/Count
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16-Bit Loadable Binary Counter - 2
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O9.T = CE & !LOAD & O8.Q & O7.Q & O
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& Q7.Q & Q6.Q & Q5.Q & Q4.Q & Q3.Q
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Serial CRC Generator using a 16-Bit
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8-Bit Loadable Data RegisterMODULE
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"dst24 = ^h05; unused state"dst25 =
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MPRSTn)MPRSTn)MPRSTn)MPRSTn)MPRSTn)
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# ((dst == dst21) & !DRAMCSn & MPRD
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MODULE m16_8High Level Implementati
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Datapath Circuit - Two repsmodule p
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Small State Machine - 8 inputs, 8 r
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state START1:if (inp1 == ^h3C) then
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module p5Arithmetic Circuit: 4 x 4
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1-Bit Accumulatormodule p6" 1--bit
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# D9 & Q8.Q);B25 = (Q11.Q & D10# D1
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A7_1.D = AS & A15 & A14 & A13 & !A1
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DRAM Refresh CounterModule refreshT
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state rfust5:state rfust6:state rfu
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Thunderbird Tailight Control Circui
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Denver International Air Traffic Co
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Appendix DError MessagesThis append
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2600 Control signals has pterms. C
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2345 File line : unknown token .C
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5030 Entries in truth table do not
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5175 Line : Constant has been decl
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3248: Pin feedback for signal is i
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Logical Errors3210: Design exceeds
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Appendix ZAbout this manualThis man
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company. It was rumored that Reno l
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