XPLA Designer v2.1 User's Manual

eg_dreg_greg_jkreg_srreg_tretainD type flip-flop clocked memory element.Gated D type flip-flop clocked memoryelement.JK type flip-flop clocked memory element.SR type flip-flop clocked memory element.T type flip-flop clocked memory element.Do not minimize this output. Preserveredundant product terms.Figure 25Multiple attributes may be specified for a particular signal as long as they do not conflictwith one another. For example:output1 PIN ISTYPE ‘reg_d, buffer, retain’;specifies the signal output1 to use a D type flip-flop with no inversion after the registerand to preserve any redundant product terms that make up the signal. However, the lineoutput1 PIN ISTYPE ‘com, invert, buffer’;is illegal because the output cannot be inverted and non-inverted at the same time. Allattributes must be separated by commas and the string of attributes must be enclosed withsingle tick (‘ ‘) marks.Bi-Directional SignalsBi-directional signals are supported on all Philips CPLDs. The multi-function input/outputpins can support bi-directional signals with the output enable of the output buffer. Whenthe output enable is turned on, the pin is an output; when the output enable is off, the pincan be used as an input. Care should be taken when using bi-directional pins to ensurethat input signals are not applied until the output enable has been turned off and the devicehas had sufficient time for the output buffer to be disabled.Bi-directional pins are not explicitly declared as input/output, but are created by the way inwhich the design is written. Take the following eight bit loadable counter example inwhich the counter output pins are also used to load the counter.Module bidi8bitTitle 'Eight bit counter with bi-directional pins'p1,p2,p3,p4,p5,p6,p7,p8loadpin;pin;44