XPLA Designer v2.1 User's Manual

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Dual 16-Bit Up/Down/Loadable/Enabled/Resetable Counters'MODULE cntr2_16title '2 16 bit up/down/loadable/enabled/resetable counters'"NOTE: reset is load & count_enab & dir.""NOTE: BIDIR pins are used for the load of each counter"DECLARATIONSdir pin 1;load pin 2;count_enab pin 44;clk pin 43;ca15..ca0cb15..cb0pin 4,5,6,7,8,9,11,12,13,14,16,17,18,19,20,21 istype 'reg';pin 41,40,39,38,37,36,34,33,32,31,29,28,27,26,25,24 istype 'reg';ca = [ca15..ca0];cb = [cb15..cb0];EQUATIONSca.clk = clk;cb.clk = clk;ca.ar = load & count_enab & dir;cb.ar = load & count_enab & dir;ca.oe = !load;cb.oe = !load;when (load == 1) then{ca.d := ca.pin;cb.d := cb.pin;}else{when (count_enab == 1) then{when (dir == 0) then{ca.d := ca.q + 1;cb.d := cb.q + 1;}182
}}else{}else when (dir == 1) then{ca.d := ca.q - 1;cb.d := cb.q - 1;}ca.d = ca.q;cb.d = cb.q;END183
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XPLA Designer
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XPLA Designer version 2.1 User’s
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SCL Brief .........................
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ARITHMETIC CIRCUIT: 4 X 4 MULTIPLIE
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the user through this design proces
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Device FittingDevice fitting is whe
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Chapter 2 Installing XPLA DesignerS
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Chapter 3XPLA TM Architecture Overv
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The XPLA TM architecture is very ac
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5ProgrammableANDArray55...Figure 6S
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Chapter 4Getting Started with XPLA
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New design filenames must use a .ph
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the CPLD utilization and pinout. Th
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more information. The simulator is
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defined without returning to the Ch
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Using the ProgrammerIf a programmer
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Reserved WordsThe following keyword
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Order of OperationsFigure 21 define
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Header SectionThe header section of
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The header of all PHDL files must s
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Module macrotstTitle 'Using macro t
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dirloadcount_enabclkpin;pin;pin;pin
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"Declare the outputscount_out = [p1
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is illegal because buried1 cannot b
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"Create a variable for counter outp
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MODULE adderTITLE ‘Two four bit a
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n1 = q3.q & q2.q;count.ar = rst # n
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dir pin;c15..c0pin istype 'reg';"De
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in them directing the state diagram
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5055606570758085state s2:when (BRAK
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[input state 3] :> [output state 3]
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if (TL ) then s3else if (TR) then s
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The simulator utilizes five logic l
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Figure 33Description of Simulator m
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This command allows the operator to
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Figure 37Del SignalThis command wil
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Add BusThis command will allow the
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Figure 43Set ValueThis command allo
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Figure 45Figure 4677
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Figure 4879
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Figure 50Transition CheckThis comma
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Figure 52To measure the difference
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• Events [+, -]• Create [Bus, C
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Figure 61Press the Create Bus butto
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Figure 68• Practice Design Simula
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Figure 74The Demo design comes with
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Figure 76Now click on the run butto
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Statements that handle signals, dat
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DescriptionFormatPT Print Title PT
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Chapter 7 Controlling the Fitting P
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wide logic functions using 1 or up
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MODULE count_16TITLE '16-bit Loadab
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Figure 88As one can see from Figure
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that may be summed for any macrocel
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Chapter 8PHDL Language ReferenceThe
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a,b,c,doutpin;pin istype 'com,inver
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when (in1 == 1) & (in2 == 1) then o
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equationsDescriptionThe reserved wo
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state [1,1]: goto [0,0];endif-then-
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Multiple if-then-else structureModu
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endistypeDescriptionThe istype stat
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macroDescriptionThe reserved word m
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signal_namenode istype ‘attribute
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XPLA property 'dut on';inoutpin;pin
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State indicates the state that is b
Page 131 and 132: state [0,1]: out = 1;if (in1 == 1)
Page 133 and 134: Module whenthenTitle 'Example of si
Page 135 and 136: out1.c = clk;out2.c = clk;when (in1
Page 137 and 138: out.c = clk;s1.c = clk;state_diagra
Page 139 and 140: Figure 92 shows the simulation mode
Page 141 and 142: * Simple SCL file (any comment is O
Page 143 and 144: Data Fields1. A data field consists
Page 145 and 146: 3-State (pull-up or pull-down) resi
Page 147 and 148: This process is repeated until all
Page 149 and 150: FFinishFormatFThe Finish command te
Page 151 and 152: IFVCondition Check on a VariableFor
Page 153 and 154: Example:||SU TIME = 10000LIST UNDEF
Page 155 and 156: This command is used to reinitializ
Page 157 and 158: B set to 1C set to 0D set to 1* Now
Page 159 and 160: SU TIME = *+500Assuming an actual t
Page 161 and 162: Appendix BDevice Pin Out Configurat
Page 163 and 164: PZ3064/PZ5064 44 Pin PLCCPin Name N
Page 165 and 166: PZ3064/PZ5064 68 Pin PLCCPin Name N
Page 167 and 168: PZ3064/PZ5064 100 Pin PQFPPIN NAME
Page 173 and 174: 8-Bit Shift RegisterModule _8bshift
Page 175 and 176: 8-Bit Adder - High LevelMODULE adde
Page 177 and 178: 4-Bit Adder with Carry in and Carry
Page 179 and 180: Bidirectional I/O’sMODULE bidirec
Page 181: 16-Bit Counter - Low Levelmodule cn
Page 185 and 186: 16-Bit Gray Code Countermodule gcnt
Page 187 and 188: & !q5 & !q4 & !q3 & !q2 & !q1 & !q0
Page 189 and 190: & q5 & !q4 & !q3 & !q2 & !q1 & !q0
Page 191 and 192: 4-Bit Gray Code Countermodule gray4
Page 193 and 194: Timer/Countermodule p2" Timer/Count
Page 195 and 196: 16-Bit Loadable Binary Counter - 2
Page 197 and 198: O9.T = CE & !LOAD & O8.Q & O7.Q & O
Page 199 and 200: & Q7.Q & Q6.Q & Q5.Q & Q4.Q & Q3.Q
Page 201 and 202: Serial CRC Generator using a 16-Bit
Page 203 and 204: 8-Bit Loadable Data RegisterMODULE
Page 205 and 206: "dst24 = ^h05; unused state"dst25 =
Page 207 and 208: MPRSTn)MPRSTn)MPRSTn)MPRSTn)MPRSTn)
Page 209 and 210: # ((dst == dst21) & !DRAMCSn & MPRD
Page 211 and 212: MODULE m16_8High Level Implementati
Page 213 and 214: Datapath Circuit - Two repsmodule p
Page 215 and 216: Small State Machine - 8 inputs, 8 r
Page 217 and 218: state START1:if (inp1 == ^h3C) then
Page 219 and 220: module p5Arithmetic Circuit: 4 x 4
Page 221 and 222: 1-Bit Accumulatormodule p6" 1--bit
Page 223 and 224: # D9 & Q8.Q);B25 = (Q11.Q & D10# D1
Page 225 and 226: A7_1.D = AS & A15 & A14 & A13 & !A1
Page 227 and 228: DRAM Refresh CounterModule refreshT
Page 229 and 230: state rfust5:state rfust6:state rfu
Page 231 and 232: Thunderbird Tailight Control Circui
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Denver International Air Traffic Co
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Appendix DError MessagesThis append
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2600 Control signals has pterms. C
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2345 File line : unknown token .C
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5030 Entries in truth table do not
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5175 Line : Constant has been decl
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3248: Pin feedback for signal is i
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Logical Errors3210: Design exceeds
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Appendix ZAbout this manualThis man
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company. It was rumored that Reno l
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