Variables are shorthand references to groups of other identifiers. Lines 16 and 17 ofFigure 22 show examples of variables. The identifiers ca15 through ca0 and cb15 throughcb0 declared in lines 13 and 14 represent the 16 bits of each counter and are assigned topins. The variables ca and cb are assigned to the strings of counter bits and can be used tosimplify the logic description section. Consider line 21 of Figure 22. Because of thevariable declaration on line 16, clocks can be assigned to all the counter outputs with thesingle lineca.clk = clk;.If the variable ca had not been declared, line 22 would have to be replaced with thefollowing 16 lines to achieve the same result:ca15.clk = clk;ca14.clk = clk;ca13.clk = clk;ca12.clk = clk;ca11.clk = clk;ca10.clk = clk;ca9.clk = clk;ca8.clk = clk;ca7.clk = clk;ca6.clk = clk;ca5.clk = clk;ca4.clk = clk;ca3.clk = clk;ca2.clk = clk;ca1.clk = clk;ca0.clk = clk;Macro FunctionsMacro functions are useful for including functions in a PHDL file several times withouthaving to retype the code each time the function is used. One can think of a macro as apre-defined function that can be called many times, each time with different signals. Forexample, if a design used three separate eight bit to three bit encoders, you would notwant to have to retype the encoding definition three separate times. You could insteaddefine the encoding in a macro and then call the macro three separate times with threeseparate sets of signals. The following example illustrates this concept.40
Module macrotstTitle 'Using macro to for three separate 8b to 3b encoders'5DECLARATIONS"Eight bit inputs to encoders10a7..a0b7..b0c7..c0pin;pin;pin;"Three bit encoded outputs15aout2..aout0 pin istype 'com,buffer';bout2..bout0 pin istype 'com,buffer';cout2..cout0 pin istype 'com,buffer';"Create the macro202530encode macro (a7,a6,a5,a4,a3,a2,a1,a0,aout2,aout1,aout0){truth_table ([?a7,?a6,?a5,?a4,?a3,?a2,?a1,?a0] -> [?aout2,?aout1,?aout0])[ 0, 0, 0, 0, 0, 0, 0, 1 ] -> [0,0,0];[ 0, 0, 0, 0, 0, 0, 1, 0 ] -> [0,0,1];[ 0, 0, 0, 0, 0, 1, 0, 0 ] -> [0,1,0];[ 0, 0, 0, 0, 1, 0, 0, 0 ] -> [0,1,1];[ 0, 0, 0, 1, 0, 0, 0, 0 ] -> [1,0,0];[ 0, 0, 1, 0, 0, 0, 0, 0 ] -> [1,0,1];[ 0, 1, 0, 0, 0, 0, 0, 0 ] -> [1,1,0];[ 1, 0, 0, 0, 0, 0, 0, 0 ] -> [1,1,1];};"Create three separate encoders using the macro35encode (a7,a6,a5,a4,a3,a2,a1,a0,aout2,aout1,aout0);encode (b7,b6,b5,b4,b3,b2,b1,b0,bout2,bout1,bout0);encode (c7,c6,c5,c4,c3,c2,c1,c0,cout2,cout1,cout0);end40Figure 2441
- Page 1 and 2: XPLA Designer
- Page 3 and 4: XPLA Designer version 2.1 User’s
- Page 5 and 6: SCL Brief .........................
- Page 7 and 8: ARITHMETIC CIRCUIT: 4 X 4 MULTIPLIE
- Page 9 and 10: the user through this design proces
- Page 11 and 12: Device FittingDevice fitting is whe
- Page 13 and 14: Chapter 2 Installing XPLA DesignerS
- Page 15 and 16: Chapter 3XPLA TM Architecture Overv
- Page 17 and 18: The XPLA TM architecture is very ac
- Page 19 and 20: 5ProgrammableANDArray55...Figure 6S
- Page 21 and 22: Chapter 4Getting Started with XPLA
- Page 23 and 24: New design filenames must use a .ph
- Page 25 and 26: the CPLD utilization and pinout. Th
- Page 27 and 28: more information. The simulator is
- Page 29 and 30: defined without returning to the Ch
- Page 31 and 32: Using the ProgrammerIf a programmer
- Page 33 and 34: Reserved WordsThe following keyword
- Page 35 and 36: Order of OperationsFigure 21 define
- Page 37 and 38: Header SectionThe header section of
- Page 39: The header of all PHDL files must s
- Page 43 and 44: dirloadcount_enabclkpin;pin;pin;pin
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- Page 51 and 52: MODULE adderTITLE ‘Two four bit a
- Page 53 and 54: n1 = q3.q & q2.q;count.ar = rst # n
- Page 55 and 56: dir pin;c15..c0pin istype 'reg';"De
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- Page 59 and 60: 5055606570758085state s2:when (BRAK
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- Page 63 and 64: if (TL ) then s3else if (TR) then s
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- Page 67 and 68: Figure 33Description of Simulator m
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- Page 77 and 78: Figure 45Figure 4677
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- Page 83 and 84: Figure 52To measure the difference
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Figure 74The Demo design comes with
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Figure 76Now click on the run butto
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Statements that handle signals, dat
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DescriptionFormatPT Print Title PT
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Chapter 7 Controlling the Fitting P
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wide logic functions using 1 or up
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MODULE count_16TITLE '16-bit Loadab
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Figure 88As one can see from Figure
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that may be summed for any macrocel
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Chapter 8PHDL Language ReferenceThe
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a,b,c,doutpin;pin istype 'com,inver
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when (in1 == 1) & (in2 == 1) then o
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equationsDescriptionThe reserved wo
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state [1,1]: goto [0,0];endif-then-
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Multiple if-then-else structureModu
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endistypeDescriptionThe istype stat
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macroDescriptionThe reserved word m
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signal_namenode istype ‘attribute
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XPLA property 'dut on';inoutpin;pin
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State indicates the state that is b
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state [0,1]: out = 1;if (in1 == 1)
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Module whenthenTitle 'Example of si
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out1.c = clk;out2.c = clk;when (in1
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out.c = clk;s1.c = clk;state_diagra
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Figure 92 shows the simulation mode
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* Simple SCL file (any comment is O
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Data Fields1. A data field consists
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3-State (pull-up or pull-down) resi
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This process is repeated until all
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FFinishFormatFThe Finish command te
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IFVCondition Check on a VariableFor
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Example:||SU TIME = 10000LIST UNDEF
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This command is used to reinitializ
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B set to 1C set to 0D set to 1* Now
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SU TIME = *+500Assuming an actual t
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Appendix BDevice Pin Out Configurat
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PZ3064/PZ5064 44 Pin PLCCPin Name N
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PZ3064/PZ5064 68 Pin PLCCPin Name N
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PZ3064/PZ5064 100 Pin PQFPPIN NAME
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PZ3128/PZ5128 100 Pin PQFPPIN NAME
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PZ3128/PZ5128 160 Pin PQFPPIN NAME
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8-Bit Shift RegisterModule _8bshift
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8-Bit Adder - High LevelMODULE adde
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4-Bit Adder with Carry in and Carry
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Bidirectional I/O’sMODULE bidirec
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16-Bit Counter - Low Levelmodule cn
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}}else{}else when (dir == 1) then{c
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16-Bit Gray Code Countermodule gcnt
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& !q5 & !q4 & !q3 & !q2 & !q1 & !q0
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& q5 & !q4 & !q3 & !q2 & !q1 & !q0
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4-Bit Gray Code Countermodule gray4
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Timer/Countermodule p2" Timer/Count
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16-Bit Loadable Binary Counter - 2
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O9.T = CE & !LOAD & O8.Q & O7.Q & O
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& Q7.Q & Q6.Q & Q5.Q & Q4.Q & Q3.Q
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Serial CRC Generator using a 16-Bit
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8-Bit Loadable Data RegisterMODULE
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"dst24 = ^h05; unused state"dst25 =
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MPRSTn)MPRSTn)MPRSTn)MPRSTn)MPRSTn)
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# ((dst == dst21) & !DRAMCSn & MPRD
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MODULE m16_8High Level Implementati
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Datapath Circuit - Two repsmodule p
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Small State Machine - 8 inputs, 8 r
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state START1:if (inp1 == ^h3C) then
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module p5Arithmetic Circuit: 4 x 4
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1-Bit Accumulatormodule p6" 1--bit
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# D9 & Q8.Q);B25 = (Q11.Q & D10# D1
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A7_1.D = AS & A15 & A14 & A13 & !A1
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DRAM Refresh CounterModule refreshT
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state rfust5:state rfust6:state rfu
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Thunderbird Tailight Control Circui
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Denver International Air Traffic Co
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Appendix DError MessagesThis append
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2600 Control signals has pterms. C
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2345 File line : unknown token .C
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5030 Entries in truth table do not
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5175 Line : Constant has been decl
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3248: Pin feedback for signal is i
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Logical Errors3210: Design exceeds
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Appendix ZAbout this manualThis man
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company. It was rumored that Reno l