XPLA Designer v2.1 User's Manual

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MODULE tbirdTITLE 'thunderbird tailight demo'5101520BRAKE pin ;TL pin ;TR pin ;CLK pin ;L1..L3 pin istype 'reg';R1..R3 pin istype 'reg';q2..q0 pin istype 'reg' ;out = [L3, L2, L1, R1, R2, R3];sreg = [q2, q1, q0] ;s0 = [0, 0, 0] ;s1 = [0, 0, 1] ;s2 = [0, 1, 0] ;s3 = [0, 1, 1] ;s4 = [1, 0, 0] ;s5 = [1, 0, 1] ;s6 = [1, 1, 0] ;s7 = [1, 1, 1] ;equations2530sreg.clk = CLK ;out.clk = CLK ;state_diagram sreg ;state s0:when (BRAKE == 0) then {out := ^b000000;} “equationselse when (BRAKE == 1 &TL == 1) then {out := ^b000111;}else when (BRAKE == 1 & TR == 1) then {out := ^b111000;}else {out := ^b111111;}354045if (TL ) then s1else if (TR) then s4else s0;state s1:when (BRAKE == 0) then {out := ^b001000;}else {out := ^b001111;}if (TL ) then s2else if (TR) then s4else s0;“state transition logic“equations“state transition logic58
5055606570758085state s2:when (BRAKE == 0) then {out := ^b011000;}else {out := ^b011111;}if (TL ) then s3else if (TR) then s4else s0;state s3:when (BRAKE == 0) then {out := ^b111000;}else {out := ^b111111;}if (TL ) then s0else if (TR) then s4else s0;state s4:when (BRAKE == 0) then {out := ^b000100;}else {out := ^b111100;}if (TR) then s5else if (TL ) then s1else s0;state s5:when (BRAKE == 0) then {out := ^b000110;}else {out := ^b111110;}if (TR) then s6else if (TL ) then s1else s0;state s6:when (BRAKE == 0) then {out := ^b000111;}else {out := ^b111111;}if (TR) then s0else if (TL ) then s1else s0;“equations“state transition logic“equations“state transition logic“equations“state transition logic“equations“state transition logic“equations“state transition logicstate s7:goto s0; "Illegal state recovery “state transition logic90END59
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XPLA Designer
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XPLA Designer version 2.1 User’s
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SCL Brief .........................
Page 7 and 8: ARITHMETIC CIRCUIT: 4 X 4 MULTIPLIE
Page 9 and 10: the user through this design proces
Page 11 and 12: Device FittingDevice fitting is whe
Page 13 and 14: Chapter 2 Installing XPLA DesignerS
Page 15 and 16: Chapter 3XPLA TM Architecture Overv
Page 17 and 18: The XPLA TM architecture is very ac
Page 19 and 20: 5ProgrammableANDArray55...Figure 6S
Page 21 and 22: Chapter 4Getting Started with XPLA
Page 23 and 24: New design filenames must use a .ph
Page 25 and 26: the CPLD utilization and pinout. Th
Page 27 and 28: more information. The simulator is
Page 29 and 30: defined without returning to the Ch
Page 31 and 32: Using the ProgrammerIf a programmer
Page 33 and 34: Reserved WordsThe following keyword
Page 35 and 36: Order of OperationsFigure 21 define
Page 37 and 38: Header SectionThe header section of
Page 39 and 40: The header of all PHDL files must s
Page 41 and 42: Module macrotstTitle 'Using macro t
Page 43 and 44: dirloadcount_enabclkpin;pin;pin;pin
Page 45 and 46: "Declare the outputscount_out = [p1
Page 47 and 48: is illegal because buried1 cannot b
Page 49 and 50: "Create a variable for counter outp
Page 51 and 52: MODULE adderTITLE ‘Two four bit a
Page 53 and 54: n1 = q3.q & q2.q;count.ar = rst # n
Page 55 and 56: dir pin;c15..c0pin istype 'reg';"De
Page 57: in them directing the state diagram
Page 61 and 62: [input state 3] :> [output state 3]
Page 63 and 64: if (TL ) then s3else if (TR) then s
Page 65 and 66: The simulator utilizes five logic l
Page 67 and 68: Figure 33Description of Simulator m
Page 69 and 70: This command allows the operator to
Page 71 and 72: Figure 37Del SignalThis command wil
Page 73 and 74: Add BusThis command will allow the
Page 75 and 76: Figure 43Set ValueThis command allo
Page 77 and 78: Figure 45Figure 4677
Page 79 and 80: Figure 4879
Page 81 and 82: Figure 50Transition CheckThis comma
Page 83 and 84: Figure 52To measure the difference
Page 85 and 86: • Events [+, -]• Create [Bus, C
Page 87 and 88: Figure 61Press the Create Bus butto
Page 89 and 90: Figure 68• Practice Design Simula
Page 91 and 92: Figure 74The Demo design comes with
Page 93 and 94: Figure 76Now click on the run butto
Page 95 and 96: Statements that handle signals, dat
Page 97 and 98: DescriptionFormatPT Print Title PT
Page 99 and 100: Chapter 7 Controlling the Fitting P
Page 101 and 102: wide logic functions using 1 or up
Page 103 and 104: MODULE count_16TITLE '16-bit Loadab
Page 105 and 106: Figure 88As one can see from Figure
Page 107 and 108: that may be summed for any macrocel
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Chapter 8PHDL Language ReferenceThe
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a,b,c,doutpin;pin istype 'com,inver
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when (in1 == 1) & (in2 == 1) then o
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equationsDescriptionThe reserved wo
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state [1,1]: goto [0,0];endif-then-
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Multiple if-then-else structureModu
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endistypeDescriptionThe istype stat
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macroDescriptionThe reserved word m
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signal_namenode istype ‘attribute
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XPLA property 'dut on';inoutpin;pin
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State indicates the state that is b
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state [0,1]: out = 1;if (in1 == 1)
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Module whenthenTitle 'Example of si
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out1.c = clk;out2.c = clk;when (in1
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out.c = clk;s1.c = clk;state_diagra
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Figure 92 shows the simulation mode
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* Simple SCL file (any comment is O
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Data Fields1. A data field consists
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3-State (pull-up or pull-down) resi
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This process is repeated until all
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FFinishFormatFThe Finish command te
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IFVCondition Check on a VariableFor
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Example:||SU TIME = 10000LIST UNDEF
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This command is used to reinitializ
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B set to 1C set to 0D set to 1* Now
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SU TIME = *+500Assuming an actual t
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Appendix BDevice Pin Out Configurat
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PZ3064/PZ5064 44 Pin PLCCPin Name N
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PZ3064/PZ5064 68 Pin PLCCPin Name N
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PZ3064/PZ5064 100 Pin PQFPPIN NAME
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8-Bit Shift RegisterModule _8bshift
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8-Bit Adder - High LevelMODULE adde
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4-Bit Adder with Carry in and Carry
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Bidirectional I/O’sMODULE bidirec
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16-Bit Counter - Low Levelmodule cn
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}}else{}else when (dir == 1) then{c
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16-Bit Gray Code Countermodule gcnt
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& !q5 & !q4 & !q3 & !q2 & !q1 & !q0
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& q5 & !q4 & !q3 & !q2 & !q1 & !q0
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4-Bit Gray Code Countermodule gray4
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Timer/Countermodule p2" Timer/Count
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16-Bit Loadable Binary Counter - 2
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O9.T = CE & !LOAD & O8.Q & O7.Q & O
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& Q7.Q & Q6.Q & Q5.Q & Q4.Q & Q3.Q
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Serial CRC Generator using a 16-Bit
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8-Bit Loadable Data RegisterMODULE
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"dst24 = ^h05; unused state"dst25 =
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MPRSTn)MPRSTn)MPRSTn)MPRSTn)MPRSTn)
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# ((dst == dst21) & !DRAMCSn & MPRD
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MODULE m16_8High Level Implementati
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Datapath Circuit - Two repsmodule p
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Small State Machine - 8 inputs, 8 r
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state START1:if (inp1 == ^h3C) then
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module p5Arithmetic Circuit: 4 x 4
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1-Bit Accumulatormodule p6" 1--bit
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# D9 & Q8.Q);B25 = (Q11.Q & D10# D1
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A7_1.D = AS & A15 & A14 & A13 & !A1
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DRAM Refresh CounterModule refreshT
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state rfust5:state rfust6:state rfu
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Thunderbird Tailight Control Circui
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Denver International Air Traffic Co
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Appendix DError MessagesThis append
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2600 Control signals has pterms. C
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2345 File line : unknown token .C
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5030 Entries in truth table do not
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5175 Line : Constant has been decl
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3248: Pin feedback for signal is i
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Logical Errors3210: Design exceeds
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Appendix ZAbout this manualThis man
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company. It was rumored that Reno l
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