XPLA Designer v2.1 User's Manual

Chapter 1Introduction to XPLA DesignerWelcome to the Philips XPLA Designer Manual! This manual provides the informationyou need to use XPLA Designer to successfully design with Philips CoolRunner CPLDs.The overall CPLD design process consists of five steps: design definition, functionalsimulation, device fitting, post layout (timing) simulation, and programming. The XPLADesigner provides the first four of these five design steps and also supports the final stepby producing a JEDEC file which can be used by most industry programmers to configurethe device. The XPLA Designer also produces Verilog and VHDL timing models whichcan be used in board level simulations. This manual provides an overview of the XPLAArchitecture and a quick tutorial on how to use XPLA Designer to assist the reader inbecoming familiar with Philips CPLDs and the XPLA Designer, respectively.The explanations and examples used in this manual assume that the user has at least somefamiliarity with Microsoft Windows and CPLDs. This manual is intended to be both areference manual for experienced users and a comprehensive instruction manual forbeginners. Each section of this manual describes a step of the design process used whentargeting Philips CPLDs. Examples in each section illustrate the concepts being discussed.Depending on your level of experience, you may wish to read through the entire manual orto study only specific sections.Supported DevicesXPLA Designer software version 2.1 supports the following devices:PZ3032PZ5032PZ3064PZ5064PZ3128PZ5128- 32 macrocell, 3.3 Volt CPLD- 32 macrocell, 5 Volt CPLD- 64 macrocell, 3.3 Volt CPLD (Preliminary Timing Model)- 64 macrocell, 5 Volt CPLD (Preliminary Timing Model)- 128 macrocell, 3.3 Volt CPLD (Preliminary Timing Model)- 128 macrocell, 5 Volt CPLD (Preliminary Timing Model)The CPLD Design ProcessThe Philips XPLA Designer is a stand-alone tool which includes all aspects of the designprocess including design definition, functional simulation, device fitting, post layout(timing) simulation and also produces a JEDEC file which can be used to program thedevice. Figure 1 shows the high-level CPLD design process. The following sections walk8