XPLA Designer v2.1 User's Manual

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" Use the macro in the designlgc_dsn (a,b,d,e,o6,o5);lgc_dsn (d,e,f,g,o1,o3);lgc_dsn (a,c,e,g,o2,o4);endmoduleDescriptionThe reserved word module is used to assign a name to the PHDL design. Module and aname for the design are required as the first line in every PHDL source.Syntaxmodule module_nameExampleModule modl_exTitle 'Example of the reserved word module'inoutpin;pin istype 'com';equationsout = in;endnodeDescriptionThe reserved word node is used to declare a signal as type node. Refer to the signalssection in chapter 5 for more information on nodes.Syntax124
signal_namenode istype ‘attributes’;Signal_name is the name assigned to the signal, and attributes are identifiers thatdetermine the type of signal. Refer to the istype description for more information.ExampleModule node_exTitle 'Example of node use'in1,in2 pin;clk pin;out pin istype 'com';n1,n2 node istype 'reg';equationsn1.c = clk;n2.c = clk;state_diagram [n1,n2]state [0,0]: out = 0;if (in1 == 1) then [0,1];state [0,1]: out = in2;if (in1 == 0) then [1,0];state [1,0]: out = 1;if (in2 == 1) then [1,1];state [1,1]: out = in1;if (in2 == 0) then [0,0];endpinDescriptionThe reserved word pin is used to declare a signal as type pin. Refer to the signals sectionin chapter 5 for more information on pins.Syntaxsignal_namepin istype ‘attributes’;125
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XPLA Designer
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XPLA Designer version 2.1 User’s
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SCL Brief .........................
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ARITHMETIC CIRCUIT: 4 X 4 MULTIPLIE
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the user through this design proces
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Device FittingDevice fitting is whe
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Chapter 2 Installing XPLA DesignerS
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Chapter 3XPLA TM Architecture Overv
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The XPLA TM architecture is very ac
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5ProgrammableANDArray55...Figure 6S
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Chapter 4Getting Started with XPLA
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New design filenames must use a .ph
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the CPLD utilization and pinout. Th
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more information. The simulator is
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defined without returning to the Ch
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Using the ProgrammerIf a programmer
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Reserved WordsThe following keyword
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Order of OperationsFigure 21 define
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Header SectionThe header section of
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The header of all PHDL files must s
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Module macrotstTitle 'Using macro t
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dirloadcount_enabclkpin;pin;pin;pin
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"Declare the outputscount_out = [p1
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is illegal because buried1 cannot b
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"Create a variable for counter outp
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MODULE adderTITLE ‘Two four bit a
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n1 = q3.q & q2.q;count.ar = rst # n
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dir pin;c15..c0pin istype 'reg';"De
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in them directing the state diagram
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5055606570758085state s2:when (BRAK
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[input state 3] :> [output state 3]
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if (TL ) then s3else if (TR) then s
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The simulator utilizes five logic l
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Figure 33Description of Simulator m
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This command allows the operator to
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Figure 37Del SignalThis command wil
Page 73 and 74: Add BusThis command will allow the
Page 75 and 76: Figure 43Set ValueThis command allo
Page 77 and 78: Figure 45Figure 4677
Page 79 and 80: Figure 4879
Page 81 and 82: Figure 50Transition CheckThis comma
Page 83 and 84: Figure 52To measure the difference
Page 85 and 86: • Events [+, -]• Create [Bus, C
Page 87 and 88: Figure 61Press the Create Bus butto
Page 89 and 90: Figure 68• Practice Design Simula
Page 91 and 92: Figure 74The Demo design comes with
Page 93 and 94: Figure 76Now click on the run butto
Page 95 and 96: Statements that handle signals, dat
Page 97 and 98: DescriptionFormatPT Print Title PT
Page 99 and 100: Chapter 7 Controlling the Fitting P
Page 101 and 102: wide logic functions using 1 or up
Page 103 and 104: MODULE count_16TITLE '16-bit Loadab
Page 105 and 106: Figure 88As one can see from Figure
Page 107 and 108: that may be summed for any macrocel
Page 109 and 110: Chapter 8PHDL Language ReferenceThe
Page 111 and 112: a,b,c,doutpin;pin istype 'com,inver
Page 113 and 114: when (in1 == 1) & (in2 == 1) then o
Page 115 and 116: equationsDescriptionThe reserved wo
Page 117 and 118: state [1,1]: goto [0,0];endif-then-
Page 119 and 120: Multiple if-then-else structureModu
Page 121 and 122: endistypeDescriptionThe istype stat
Page 123: macroDescriptionThe reserved word m
Page 127 and 128: XPLA property 'dut on';inoutpin;pin
Page 129 and 130: State indicates the state that is b
Page 131 and 132: state [0,1]: out = 1;if (in1 == 1)
Page 133 and 134: Module whenthenTitle 'Example of si
Page 135 and 136: out1.c = clk;out2.c = clk;when (in1
Page 137 and 138: out.c = clk;s1.c = clk;state_diagra
Page 139 and 140: Figure 92 shows the simulation mode
Page 141 and 142: * Simple SCL file (any comment is O
Page 143 and 144: Data Fields1. A data field consists
Page 145 and 146: 3-State (pull-up or pull-down) resi
Page 147 and 148: This process is repeated until all
Page 149 and 150: FFinishFormatFThe Finish command te
Page 151 and 152: IFVCondition Check on a VariableFor
Page 153 and 154: Example:||SU TIME = 10000LIST UNDEF
Page 155 and 156: This command is used to reinitializ
Page 157 and 158: B set to 1C set to 0D set to 1* Now
Page 159 and 160: SU TIME = *+500Assuming an actual t
Page 161 and 162: Appendix BDevice Pin Out Configurat
Page 163 and 164: PZ3064/PZ5064 44 Pin PLCCPin Name N
Page 165 and 166: PZ3064/PZ5064 68 Pin PLCCPin Name N
Page 167 and 168: PZ3064/PZ5064 100 Pin PQFPPIN NAME
Page 173 and 174: 8-Bit Shift RegisterModule _8bshift
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8-Bit Adder - High LevelMODULE adde
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4-Bit Adder with Carry in and Carry
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Bidirectional I/O’sMODULE bidirec
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16-Bit Counter - Low Levelmodule cn
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}}else{}else when (dir == 1) then{c
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16-Bit Gray Code Countermodule gcnt
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& !q5 & !q4 & !q3 & !q2 & !q1 & !q0
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& q5 & !q4 & !q3 & !q2 & !q1 & !q0
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4-Bit Gray Code Countermodule gray4
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Timer/Countermodule p2" Timer/Count
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16-Bit Loadable Binary Counter - 2
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O9.T = CE & !LOAD & O8.Q & O7.Q & O
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& Q7.Q & Q6.Q & Q5.Q & Q4.Q & Q3.Q
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Serial CRC Generator using a 16-Bit
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8-Bit Loadable Data RegisterMODULE
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"dst24 = ^h05; unused state"dst25 =
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MPRSTn)MPRSTn)MPRSTn)MPRSTn)MPRSTn)
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# ((dst == dst21) & !DRAMCSn & MPRD
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MODULE m16_8High Level Implementati
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Datapath Circuit - Two repsmodule p
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Small State Machine - 8 inputs, 8 r
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state START1:if (inp1 == ^h3C) then
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module p5Arithmetic Circuit: 4 x 4
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1-Bit Accumulatormodule p6" 1--bit
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# D9 & Q8.Q);B25 = (Q11.Q & D10# D1
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A7_1.D = AS & A15 & A14 & A13 & !A1
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DRAM Refresh CounterModule refreshT
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state rfust5:state rfust6:state rfu
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Thunderbird Tailight Control Circui
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Denver International Air Traffic Co
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Appendix DError MessagesThis append
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2600 Control signals has pterms. C
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2345 File line : unknown token .C
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5030 Entries in truth table do not
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5175 Line : Constant has been decl
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3248: Pin feedback for signal is i
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Logical Errors3210: Design exceeds
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Appendix ZAbout this manualThis man
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company. It was rumored that Reno l
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