iAPX 286 Operating System Writers Guide 1983

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DATA SHARING, ALIASING, AND SYNCHRONIZATIONOTHER FORMS OF SYNCHRONIZATIONYou may wish to implement other forms of synchronization; for example:• Conditional variation of WAIT_SEMAPHORE that does not force a task to wait when the semaphorehas not been signalled.• Timed waiting, so that a task can be awakened if the semaphore is not signalled within a reasonabletime. (This helps guard against deadlocks.)• An extension of the semaphore concept known as a region. A region is similar to a semaphore exceptthat only the task that acquires a: region can release (signal) it, and a task that holds a region cannotbe suspended.MESSAGE PASSINGMessage passing is a general purpose means for transferring data from the address space of one taskto the address space of another, cooperating task. There are two aspects to the technique:• Transferring data from a segment in one task's address space into a segment in the receiving task'sspace• Transferring a segment from one task's space into another'sThe first case is suitable for passing relatively small amounts of data, such as parameters, informationdescribing events, etc. The second case has two primary applications:• For transferring large "consumable resources" such as I/0 buffers• For transferring aliases that implement the previously described method of "sharing via aliases"When an alias is passed as part of a message, the operating system installs the alias in a descriptortableslot determined by the receiving task.Message-Passing ExampleFigure 5-6 shows an example data structure for implementing a simple form of message passing. Thisstructure defines a mailbox, a queue of tasks waiting for messages from the mailbox, and a queue ofundelivered messages. The system may contain one mailbox for every communication channel betweentasks. For simplicity, this example assumes that the format of messages for all mailboxes is the same,consisting of a fixed-length data item and two descriptors.If each mailbox resides in a unique segment, then these advantages result:• Mailboxes are protected from operations on other mailboxes.• A selector can serve as the identifier of a mailbox.Only the sending and receiving tasks need access to a mailbox; therefore, the appropriate tables fordescriptors for mailbox segments are the LDTs of each of the tasks that share a mailbox. All tasks canshare a global mailbox, however, if its descriptor is in the GDT. The DPL for all mailbox segmentsshould be zero to prevent procedures outside the operating system from interfering with message passing.Mailboxes require at least two procedures: SEND_MESSAGE and RECEIVE_MESSAGE. Figure5-7 shows examples of these .procedures. Both procedures must run at PL 0 to access level-O mailbox5:-10 121960·001
DATA SHARING, ALIASING, AND SYNCHRONIZATIONSCHEDULER QUEUE SEGMENTr---------------------------,QUEUEELEMENTS IIIHEAD OFQUEUETO TASKL!.I.r1.)..LL...::t-1-- ENTRIESINGOTMAILBOXTASK QUEUEPOINTERHEAD OFMESSAGEQUEUETAIL OFMESSAGEQUEUEIIIIIIII L ___________________________ J IQUEUE OF UNDELIVERED MESSAGESr---------------------------,NEXT DATA DESCRIPTORSL ___________________________ J IFigure 5-6. Mailbox Structure121960-335-11121960-001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
Page 59 and 60: CHAPTER 3REAL MEMORY MANAGEMENTIn d
Page 61 and 62: REAL MEMORY MANAGEMENTIALLOCATEGATE
Page 63 and 64: interREAL MEMORY MANAGEMENTBEFOREAF
Page 65 and 66: REAL MEMORY MANAGEMENTGLOBAL DESCRI
Page 67 and 68: REAL MEMORY MANAGEMENTTable 3-1. Ac
Page 69 and 70: REAL MEMORY MANAGEMENTBEFOREI "FREE
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Page 73 and 74: REAL MEMORY MANAGEMENTPL/M-286 COMP
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Page 84 and 85: II I telTASK MANAGEMENTCPUTASK REGI
Page 86 and 87: TASK MANAGEMENTIf the proc~sser, wh
Page 88 and 89: TASK MANAGEMENTUsually, termination
Page 90 and 91: TASK MANAGEMENTTASK XTSS TSS TSS TS
Page 92 and 93: TASK MANAGEMENTSCHEDULING POLICIEST
Page 94 and 95: TASK MANAGEMENTThe example in figur
Page 96 and 97: TASK MANAGEMENTREADY QUEUESBY PRIOR
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Page 101 and 102: CHAPTER 5DATA SHARING, ALIASING, AN
Page 103 and 104: DATA SHARING, ALIASING, AND SYNCHRO
Page 105 and 106: interDATA SHARING, ALIASING, AND SV
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Page 121 and 122: CHAPTER 6SIGNALS AND INTERRUPTSInte
Page 123 and 124: interSIGNALS AND INTERRUPTSlOTGOTTS
Page 125 and 126: SIGNALS AND INTERRUPTSTable 6-1. In
Page 127 and 128: SIGNALS AND INTERRUPTSSend interrup
Page 129 and 130: SIGNALS AND INTERRUPTSprocedure suc
Page 131: Handling Exception Conditions 7
Page 134 and 135: HANDLING EXCEPTION CONDITIONSError
Page 136 and 137: HANDLING EXCEPTION CONDITIONSAn exc
Page 138 and 139: HANDLING EXCEPTION CONDITIONSA few
Page 140 and 141: HANDLING EXCEPTION CONDITIONSAn ins
Page 143 and 144: CHAPTER 8INPUT /OUTPUTMany of the c
Page 145 and 146: INPUT /OUTPUTYou can still take adv
Page 147 and 148: INPUT /OUTPUT• Only the operating
Page 149: INPUT /OUTPUTtask the I/0 procedure
Page 153 and 154: CHAPTER 9VIRTUAL MEMORYThe memory l
Page 155 and 156: VIRTUAL MEMORYthose segments that a
Page 157 and 158: VIRTUAL MEMORY• Return the RAM sp
Page 159 and 160: VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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interBINDING AND LOADINGsystem-IDiA
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BIND.ING AND LOADINGConverting a Pr
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BINDING AND LOADINGThe OMF of each
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interBINDING AND LOADINGsystem-IDiA
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOADI.NGPL/M-286 COMPIL
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BINDING AND LOADINGPL/M-286 COMPILE
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOAD.INGPL/M-286 COMPIL
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interBINDING AND LOADINGPL/M-286 CO
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BINDING AND LOADINGPL/M-286 COMPILE
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Numerics Processor Extension 12
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NUMERICS PROCESSOR EXTENSIONMath Pr
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interNUMERICS PROCESSOR EXTENSION
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Extended Protection13
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EXTENDED PROTECTIONIndirect NamingT
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EXTENDED PROTECTIONanother procedur
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Glossary
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GLOSSARYbootloadable module: a modu
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GLOSSARYexception: a processor-dete
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GLOSSARYintersegment reference: a r
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GLOSSARYoutward call: the attempt t
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GLOSSARYscheduling state: one of se
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GLOSSARYvirtual address: an address
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INDEXES register, 2-17, 2-18, 2-21,
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INDEXpresent bit, 2-2, 2-3, 2-9, 5-
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interu.s. SALES OFFICESALAIWIA IlEQ
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interu.s. DISTRIBUTORSNEW YORK (C"n
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intJINTEL INTERNATIONAL SALES OFFIC
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