iAPX 286 Operating System Writers Guide 1983

SIGNALS AND INTERRUPTSWhen an interrupt occurs, the processor uses the interrupt identifier as an index into the interruptdescriptor table (IDT).Enabling and Disabling InterruptsThe interrupt flag (IF) controls whether the processor immediately reacts to external events. Whenreset, IF masks out signals presented to the INTR pin. It has no effect on NMI, on processor-detectedexceptions, or on software signals (INT and INTO).To set IF, use the STI instruction (ENABLE statement in PL/M-286); to reset IF, use CLI (DISABLE).Interrupt Descriptor TableThe IDT associates each interrupt identifier with a descriptor for the instructions that process theassociated event. The IDT is similar to the GDT and LDTs but is different in two important respects:• The processor references the IDT only as the result of an interrupt.• The only descriptors permitted in the IDT are three kinds of gate descriptors: task gates, interruptgates, and trap gates (descriptor types 5-7, respectively).The IDT may dwell at any location in memory. The processor locates the IDT via the IDT register.The operating system uses the instruction LIDT (load IDT) to set the IDT register. The instructionSIDT (store IDT) reads the contents of the IDT register. There can be only one IDT, but the operatingsystem can use the LIDT instruction to substitute another array of gate descriptors.Interrupt Tasks and Interrupt ProceduresIn response to an event, the processor interrupts the currently executing task and begins executing theinstructions identified by the IDT gate descriptor that is associated with the event. The instructionsthat execute as the result of the event may either be• A task other than the current task• A procedure within the current taskIf the descriptor indexed by the interrupt identifier is a task gate, which points to a task state segment,then the processor causes a task switch. Figure 6-1 illustrates the links that identify the interrupt task.Chapter 4 discusses the mechanisms associated with task switching and considers the impact thathardware task switching has on the operating system's task scheduler.If the descriptor indexed by the interrupt identifier is either an interrupt gate or a trap gate (whichpoint to executable segments), then no task switch occurs. Instead the processor behaves similarly tothe way it would if the current task had called the indicated procedure via a call gate. Figure 6-2illustrates the links that identify the interrupt procedure. The iAPX 286 protection mechanism requireseither that the target segment have a privilege level numerically less than or equal to CPL or that thetarget segment be conforming. If one of these conditions is true, then the indicated procedure beginsexecuting in the current task. The major mechanical difference between invoking a procedure by aninterrupt and invoking by a CALL is that, with an interrupt, the processor pushes the flag word ontothe staek of the invoked procedure before the return address (as illustrated in figure 6-3) and clearsthe single-step flag (TF).6-2 121960-001