INDEXES register, 2-17, 2-18, 2-21, 2-22, 4-12,7-5thru 7-7, 9-1, 9-6, 9-7, 10-1ESCAPE instructions, 7-4, 12-1 thru 12-5EX (external) bit, 7-2. examples, 2-20 thru 2-26,3-1 thru 3-9, 3-15 thru3-21, 4-15, 5-8, 5-9, 5-13 thru 5-16, 10-3thru 10-15, 11-6 thru 11-8, 11-12 thru11-28exception, 1-7, 2-8, 2-10, 2-17, 4-3, 4-7, 5-5, 6-2,6-4, 6-9, Chapter 7, 9-1, 11-3, 13-3, 13-5handler, 6-7, Chapter 7, 9-2, 9-4, 11-3, 12-4,12-5recovery, Chapter 7, 12-3 thru 12-5EXECUTE, 11-9execute-only segment, 7-7, 13-4expand-down segment, 2-5, 11-11, 13-4expansion direction, 2-5, 5-3EXPORT,11-6export module, 11-6, 11-12, 11-13exports list, 11-4, 11-5extended segmentation controls, 11-4EXTERNAL, 3-6FAR,II-4fault, see exceptionFINIT, 12-5"first fit" algorithm, 3-1, 3-2flag word, 4-2 thru 4-4, 6-2, 6-4, 8-1, 8-2, 10-1FNINIT, 12-2, 12-5FORK,II-9fragmentation, 3-1, 3-2, 9-6FRSTOR,12-4FSAVE, 12-4, 12-5FSETPM, 12-2, 12-5gate, 2-8, 2-11, 11-6call, 2-8,2-10,2-12,2-14,2-15,2-21,3-9,4-13,5-7,5-12,6-1,6-2,8-7,11-3,11-12,11-14interrupt, 2-8, 2-15, 6-2, 6-4, 6-7name, 11-6task, 2-8, 2-14, 2-15, 4-3, 4-7, 6-2, 6-4, 7-5,10-3trap, 2-8, 2-15, 6-2, 6-4, 6-7see also descriptor, gateGATE,II-6GDT, see global descriptor tableGDT register, 2-15, 10-2general protection exception, 7"7, 8-2GEnACCESS$RIGHTS, 13-2GEnSEGMENnLIMIT, 3-6, 13-2global descriptor table (GDT), 1-3,2-12,2-14thru 2-19, 2-22, 3-3, 3-4, 3-7, 3-8, 4-1, 4-3,4-10 thru 4-12,5-1,5-7,5-10,6-7, 7-2, 8-7,10-2, 10-3, 11-2, 11-4, 11-5, 11-9 thru 11-12,13-5handler table, 6-7hashing algorithm, 5-3I bit (of error code), 7-2<strong>iAPX</strong> <strong>286</strong> Binder, 1-10, 11-3, 11-5, 11-6, 11-10,11-11<strong>iAPX</strong> <strong>286</strong> <strong>System</strong> Builder, 1-8 thru 1-11, 2-2,2-4, 2-12, 2-18, 3-1, 3-6, 8-2, 10-3, 11-3 thru11-6, 11-8, 11-10, 11-11<strong>iAPX</strong> 386, 2-3identifier, 5-7, 5-10, 8-7see also interrupt identifierIDT, see interrupt descriptor tableIDT register, 2-15, 6-2IF (interrupt-enable) flag, 4-6, 5.:6, 6-2, 6-4index field (of selector), 2-16,2-17,5-3,7-2INIT$REAL$MATH$UNIT,12-2initializationof 80287, 12-2see also system initializationinput/output (1/0),1-4 thru 1-7,2-18,4-5,4-7,4-10,5-10, Chapter 8, 9-2, 9-4, 9-8, 11-2,11-4, 11-9indirect, 8-3memory-mapped, 8-2IN,8-1INS, 7-7, 8-1INT, 2-7, 2-10, 2-15, 4-3, 6-1, 6-2, 7-3INT A cycles, 2-15INTO, 6-1, 6-2, 7-3INTR pin, 6-1, 6-2, 6-6interrupt, 1-4, 1-7,2-10,2-15,2-21,4-3,5-4 thru5-6, Chapter 6, 7-1, 7-6, 7-7, 8-4, 10-1,10-2distribution, 6-7 thru 6-9flag, see IFidentifier, 2-15, 6-1, 6-2handler, 2-15, 2-18, 4-6latency, see interrupt response timemask, 4-7, 12-4procedure, 4-4, 4-7, 4-11, 4-13, 6-2, 6-4 thru6-7, 7-1, 12-4response time, 4-3, 5-5, 6-5, 12-4scheduled task, see schedulingsoftware, 6-1task, 4-4, 4-7, 6-2, 6-4 thru 6-6, 7-1, 7-6, 9-4,12-4, 13-5interrupt descriptor table (IDT), 2-12, 2-15,2-16,2-18,4-3,4-5,4-7,6-2,6-4,6-5,6-7,7-2, 7-5, 10-2, 10-3, 11-11Index-2 121960-001
INDEX"invalid TSS" exception, 7-5 thru 7-7, 9-2, 9-510PL (I/O privilege level), 4-6, 5-6, 8-1, 8-2,8-5IP register, 4-4, 6-9, 7-1, 7-3, 7-5, 7-7, 10-1,11-9, 12-4, 12-5IRET, 2-7, 2-10, 4-3, 4-4, 4-13, 6-4, 6-6, 6-7, 6-9,7-3,7-5,7-7,8-2,12-5JMP, 2-5, 2-7, 2-9, 2-10, 4-3, 4-4, 4-13, 7-7,10-1, 10-3LABEL,11-4LAR, 9-7, 13-2, 13-4LARGE,11-4LDT, see local descriptor tableLDT register, 2-14, 4-3, 7-6, 9-1LDT selector (of TSS), 4-1, 4-3, 6-9, 7-5, 10-2,11-11LEAVE,7-6LGDT,2-15LIDT, 2-15, 6-2limit field (of descriptor), 2-4, 2-5, 2-12, 2-15,2-16,4-1,5-3,7-5 thru 7-7, 9-5, 10-1, 10-3,11-11,12-4,13-2,13-4linkage, 1-10, 7-6LLDT, 2-14, 7-6LMSW, 10-1,12-1loading, see program loadinglocal descriptor table (LDT), 2-5, 2-12, 2-14,2-16,2-18 thru 2-20, 3-1, 4-10, 5-1 thru 5-3,5-10,5-17,6-7,7-2,8-7,9-3,9-4,9-7,10-2,10-3, 11-2, 11-4, 11-5, 11-8 thru 11-12not present, 9-1, 9-2LOCAUTABLE,2-14LOCK,8-2LODTXT section, 11-11, 11-12logical segment, 1-1, 11-2 thru 11-5Lst, 9-7, 13-2, 13-4LTR, 4-1,9-1MACHINE$STATUS, 12-1mailbox, 5-10 thru 5-12, 5-16, 5-17, 8-7, 9-3,9-5, 11-2, 13-1, 13-4, 13-5mechanisms, see policies and mechanismsmemory managementreal, 1-8, 1-9,2-22, Chapter 3,5-4,5-12,5-17,8-3, 8-5, 11-6virtual, 1-8,2-2,2-3,2-7,7-6, Chapter 9, 11-9message, 2-19, 3-9, 4-9, 5-4, 5-10, 5-12, 5-16module, 11-1 thru 11-6bootloadable, 11-6, 11-10linkable, 11-6, 11-10load able, 1-10, 11-10, 11-11, 11-14object, 1-8, 1-9, 11-9, 11-10MOV, 7-6MOVS, 7-7MP (math present) flag, 7-4, 12-1 thru 12-4MSW (machine status word), 7-4, 7-8, 10-1,12-1, 12-2multiprocessor systems, 3-10mutual exclusion, 5-5, 5-6naming, 11-1 thru 11-6, 11-11, 11-12, 13-1, 13-2,13-4, 13-5NEAR,II-4NMI (non-maskable interrupt), 6-1, 6-2, 10-2NOT PRESENT statement, 11-12"not present" exception, 7-5 thru 7-7,9-1,9-3thru 9-8, 11-3see also present bitNT (nested task) flag, 4-2 thru 4-4, 4-7, 7-6, 9-4,11-10Numerics Processor Extension (NPX),see 80287OBJECT, 11-6object module format (OMF), 11-8, 11-10,11-11OF (overflow) flag, 7-3OUT,8-2OUTS, 7-7, 8-2outward call, 6-8overflow exception, 7-3paged architecture, 9-6parallel table, 5-3, 13-1parallelism. 1-4, 8-4, 8-7PE (protection enable) flag, 10-1Petri net graph, 8-4, 8-5physical address, 1-8, 1-9,2-4,3-2 thru 3-4,11-10physical segment, 1-1, 1-2,2-12,2-15, 11-1 thru11-3PIC, see 8259A Programmable InterruptControllerpipes, 5-17PL/M-<strong>286</strong>, 2-14 thru 2-16, 2-21, 2-22, 3-3, 3-6,4-1, 4c3, 4-13, 6-2, 11-4, 11-6, 12-2, 12-4,13-2pointer parameters, see selector parameterspolicies and mechanismsscheduling, 4-9, 4-10virtual memory management, 9-1, 9-6POP, 7-6POPA,7-7POPF,8-2preemption, 4-5, 4-7, 4-9, 4-10, 4-13prefix, 7-1Index-3 121960-001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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INTRODUCTION TO PROTECTED MULTITASK
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INTRODUCTION TO PROTECTED MULTITASK
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
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CHAPTER 3REAL MEMORY MANAGEMENTIn d
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REAL MEMORY MANAGEMENTIALLOCATEGATE
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interREAL MEMORY MANAGEMENTBEFOREAF
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REAL MEMORY MANAGEMENTGLOBAL DESCRI
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REAL MEMORY MANAGEMENTTable 3-1. Ac
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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IIIIIIIIIIIIIIIIIIIIII
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II I telTASK MANAGEMENTCPUTASK REGI
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TASK MANAGEMENTIf the proc~sser, wh
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TASK MANAGEMENTUsually, termination
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TASK MANAGEMENTTASK XTSS TSS TSS TS
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TASK MANAGEMENTSCHEDULING POLICIEST
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TASK MANAGEMENTThe example in figur
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TASK MANAGEMENTREADY QUEUESBY PRIOR
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
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CHAPTER 5DATA SHARING, ALIASING, AN
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DATA SHARING, ALIASING, AND SYNCHRO
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interDATA SHARING, ALIASING, AND SV
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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CHAPTER 6SIGNALS AND INTERRUPTSInte
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interSIGNALS AND INTERRUPTSlOTGOTTS
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SIGNALS AND INTERRUPTSTable 6-1. In
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SIGNALS AND INTERRUPTSSend interrup
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SIGNALS AND INTERRUPTSprocedure suc
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Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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interBINDING AND LOADINGsystem-IDiA
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