iAPX 286 Operating System Writers Guide 1983

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interNUMERICS PROCESSOR EXTENSION• The CPU encounters either the WAIT instruction or an ESC instruction when both MP and TS areset. In this case, the exception handler should update the state of the NPX if necessary.EMULATIONThe return link points to the first byte of the ESC instruction (or to the prefix byte, if any). As theemulator decodes the ESC instruction, it should step the return pointer so that, at the end of theemulation routine, the return from the exception handler causes execution to resume at the firstinstruction following the ESC instruction.UPDATING STATETo make sure that the state of the NPX corresponds to the current task, the operating system shouldimplement the concept of "ownership" of the NPX. Ownership can be indicated by a Boolean in thetask database (TDB). The operating system must ensure that only one task at a time is marked as theowner of the NPX. The exception handler should follow these steps:1. Use the CL TS instruction to reset TS.2. Return if the current task owns the NPX.3. Use the FSAVE ESC instruction (PL/M-286 SAVE$REAUSTATUS) to store NPX context inthe former owner's task database.4. Record the current task as the owner of the NPX.5. Use the FRSTOR ESC instruction (PL/M-286 RESTORE$REAUSTATUS) to load the NPXcontext from the new owner's TDB.Since task switches may occur during execution of the exception handler, steps 3, 4, and 5 are a criticalregion and must be protected by a mechanism such as a semaphore.The exception handler must run at PL 0, both because it alters the critical task database at PL 0 andbecause it uses the privileged instruction CL TS.The exception handler must be an interrupt procedure, not an interrupt task. If it were an interrupttask, the task switch that occurs upon returning from the exception handler would set TS, therebycausing the exception again.The return link points to the first byte of the interrupted instruction. Return from the exception handlercauses restart of that instruction, but this time TS is reset and the instruction can proceed.Interrupt 9-Processor Extension Segment Overrun (MP)This exception occurs when a memory operand of an 80287 instruction has a segment-limit violation.Since the 80287 executes in parallel with the 80286, two difficulties may arise:• The occurrence of this exception may not relate directly to the instruction stream being executedby the current task. A task switch may have occurred since the 80287 began executing the instruction.Even if the interrupted task is the correct task, its IP may have been advanced by severalinstructions beyond the ESC instruction.• Since the exception is not maskable, it may occur while interrupts are disabled. If minimum interruptlatency is important, the exception handler must do as little as possible. It could, for cxample,record the error for later handling.12-4 121960·001
NUMERICS PROCESSOR EXTENSIONThe offending ESC instruction cannot be restarted. The task containing the ESC instruction (whichmay not be the current task) must eventually be cancelled.The exception handler must execute an FINIT instruction before executing a WAIT or other ESCinstruction; otherwise, the WAIT or ESC instruction will never finish. FlNIT does not affect the CS:IPvalue and data address saved in the 80287.Note that the 80286 CPU detects some addressing violations before sending the ESC instruction tothe 80287 NPX. In these. cases, the CPU causes trap 13 (pushing an error code of zero), and it isgenerally possible to restart the ESC instruction. Refer to Chapter 7 for more information regardingtrap 13.Interrupt 16-Processor Extension Error (MF)The 80287 detects six different exception conditions during instruction execution. If the detectedexception is not masked by a bit in the control word, the 80287 communicates the fact that an erroroccurred to the CPU by a signal at the ERROR pin. The CPU causes interrupt 16 the next time itchecks the ERROR pin, which is only at the beginning of a subsequent WAIT or certain ESC instructions.If the exception is masked, the 80287 handles the exception according to on-board logic; it doesnot assert the ERROR pin in this case.The six exception conditions are1. INVALID OPERATION2. OVERFLOW3. ZERO DIVISOR4. UNDERFLOW5. DENORMALIZED OPERAND6. PRECISION (INEXACT RESULT)The steps to be taken to remove the error condition depend on the application.Once the exception handler corrects the error condition causing the exception, the floating pointinstruction that caused the exception can be restarted, if appropriate. This cannot be accomplished byIRET, however, because the trap occurs at the ESC or WAIT instruction following the offending ESCinstruction. The handler must obtain from the 80287 the address of the offending instruction in thetask that initiated it, make a copy of it, execute the copy in the context of the offending task, and thenreturn via IRET to the current CPU instruction stream.The ESC instructions that do not cause automatic checking of the ERROR pin are FNCLEX, FNINIT,FSAVE, FSETPM, FSTCW, FSTENV, and FSTSW. You can use the WAIT instruction to test theERROR pin before these instructions, if necessary.12-5 121960·001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
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CHAPTER 3REAL MEMORY MANAGEMENTIn d
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REAL MEMORY MANAGEMENTIALLOCATEGATE
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interREAL MEMORY MANAGEMENTBEFOREAF
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REAL MEMORY MANAGEMENTGLOBAL DESCRI
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REAL MEMORY MANAGEMENTTable 3-1. Ac
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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IIIIIIIIIIIIIIIIIIIIII
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II I telTASK MANAGEMENTCPUTASK REGI
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TASK MANAGEMENTIf the proc~sser, wh
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TASK MANAGEMENTUsually, termination
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TASK MANAGEMENTTASK XTSS TSS TSS TS
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TASK MANAGEMENTSCHEDULING POLICIEST
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TASK MANAGEMENTThe example in figur
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TASK MANAGEMENTREADY QUEUESBY PRIOR
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
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CHAPTER 5DATA SHARING, ALIASING, AN
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DATA SHARING, ALIASING, AND SYNCHRO
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interDATA SHARING, ALIASING, AND SV
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CHAPTER 6SIGNALS AND INTERRUPTSInte
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interSIGNALS AND INTERRUPTSlOTGOTTS
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SIGNALS AND INTERRUPTSTable 6-1. In
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SIGNALS AND INTERRUPTSSend interrup
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SIGNALS AND INTERRUPTSprocedure suc
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Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
Page 163 and 164: CHAPTER 10SYSTEM INITIALIZATIONThe
Page 165 and 166: SYSTEM INITIALIZATIONStarting the f
Page 167 and 168: iAPX286 "ACRO ASSEMBLERLOCOBJEnter
Page 169 and 170: iAPX286 MACRO ASSEMBLEtEnter Protec
Page 171 and 172: iAPX286 MACRO ASSEMBLER·· Enter ~
Page 173 and 174: iAPX286 'UCRO USE148LER Ente,. P,.o
Page 175 and 176: iAPX286 MACRO ASSEMBLEREnt9~ P~otec
Page 177: iAPX286 MACRO ASSEMBLE~ INITIAL TAS
Page 181 and 182: CHAPTER 11BINDING AND LOADINGBindin
Page 183 and 184: BINDING AND LOADINGNamingThe names
Page 185 and 186: BINDING AND LOADING$ COMPACT (NUCLE
Page 187 and 188: interBINDING AND LOADINGsystem-IDiA
Page 189 and 190: BIND.ING AND LOADINGConverting a Pr
Page 191 and 192: BINDING AND LOADINGThe OMF of each
Page 193 and 194: interBINDING AND LOADINGsystem-IDiA
Page 195 and 196: BINDING AND LOADINGPL/M-2B6 COMPILE
Page 197 and 198: BINDING AND LOADI.NGPL/M-286 COMPIL
Page 199 and 200: BINDING AND LOADINGPL/M-286 COMPILE
Page 201 and 202: BINDING AND LOADINGPL/M-2B6 COMPILE
Page 203 and 204: BINDING AND LOAD.INGPL/M-286 COMPIL
Page 205 and 206: interBINDING AND LOADINGPL/M-286 CO
Page 207 and 208: BINDING AND LOADINGPL/M-286 COMPILE
Page 209: Numerics Processor Extension 12
Page 212 and 213: NUMERICS PROCESSOR EXTENSIONMath Pr
Page 217: Extended Protection13
Page 220 and 221: EXTENDED PROTECTIONIndirect NamingT
Page 222 and 223: EXTENDED PROTECTIONanother procedur
Page 225: Glossary
Page 228 and 229: GLOSSARYbootloadable module: a modu
Page 230 and 231: GLOSSARYexception: a processor-dete
Page 232 and 233: GLOSSARYintersegment reference: a r
Page 234 and 235: GLOSSARYoutward call: the attempt t
Page 236 and 237: GLOSSARYscheduling state: one of se
Page 238 and 239: GLOSSARYvirtual address: an address
Page 240 and 241: INDEXES register, 2-17, 2-18, 2-21,
Page 242 and 243: INDEXpresent bit, 2-2, 2-3, 2-9, 5-
Page 245 and 246: interu.s. SALES OFFICESALAIWIA IlEQ
Page 247 and 248: interu.s. DISTRIBUTORSNEW YORK (C"n
Page 249 and 250: intJINTEL INTERNATIONAL SALES OFFIC
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iAPX 286 Operating System Writers Guide 1983

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