iAPX 286 Operating System Writers Guide 1983

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II I telTASK MANAGEMENTCPUTASK REGISTERTRD----15 0.... ----------,II PROGRAM INVISIBLE II 15 0 IILIMIT~}II +-III BASEI 23 0 II IL____ ______•SYSTEM--SEGMENTDESCRIPTORINTEL RESERVED~p_lir_:IO_)~_l_~~S~E~_AS_E_"_'_'~ljllLlMIT,,~ r------------------------~BYTE15 o OFFSETTASK LOT SELECTOR 42OS SELECTOR 40SS SELECTOR 38CS SELECTOR 36ES SELECTOR 3401 3251 30BP 28 CURRENTTASKSP 26 STATEBX 24TASK OX 22STATESEGMENT CX20AX 18FLAG WORD 16IP (ENTRY POINT) 14SS FOR CPL 2 12SP FOR CPL 2 1055 FOR CPL 1 8 INITIALSTACKSSP FOR CPL 1 -6 FOR CPL 0,1,2SS FOR CPL 0 4SP FOR CPL 0 2BACK LINK SELECTOR TO TSS 0Figure 4-1. Task State Segment and Register121960-23• Processor registers and flags. Used to store the processor state of the task. Note in particular theNT flag, which indicates when the BACK LINK contains a valid selector.• Initial stacks. Contain the initial SS and SP values to be used when a CALL transfers control toany of the higher PLs (0, 1, or 2). No stack pointer is needed in the TSS for the PL-3 stack becausethat stack is either the current staek (pointed to by the SS:SP fields) or is locatable via the chainof stack pointers in higher-level stacks.4-2 121960-001
TASK MANAGEMENTThe processor updates only the back link, the registers, and the flags as part of a task switching operation.The processor merely reads the initial stack fields (during interlevel CALLs) and the LDT selector(during a task switch). The operating system is responsible for initializing the stack and LDT fields.It must also update the LDT selector before changing the LDT register.Switching TasksSince a multitasking system typically has more tasks than it has processors to execute those tasks,there must be some provision for causing a processor to cease executing one task and begin executinganother. The 80<strong>286</strong> has several such mechanisms, each appropriate to different situations. All useordinary JMP, CALL, INT, or IRET instructions. The destination operand determines whether a taskswitch occurs. Table 4-1 summarizes the operations and operands that cause switching of tasks.In PL/M-<strong>286</strong>, an indirect CALL statement to the selector of a TSS descriptor or task gate causesgeneration of an intertask CALL instruction. The W AIT$FOR$INTERRUPT built-in proceduregenerates an IRET instruction.The operand of a CALL or JMP instruction is a pointer containing both selector and offset parts; inthis case, the offset is not used, however. The selector portion may refer either to the descriptor of aTSS or to a task gate for a TSS. The result is the same in either case. The difference lies in theprotection of access to the TSS. TSS descriptors, which may reside only in the GDT, normally haveDPL set to zero to prevent unauthorized task switching by procedures outside the operating system.Task gates may reside in any descriptor table, giving task switching ability to procedures that haveaccess to the gate. A task gate in an LDT gives task switching power only to that LDT's task. A taskgate in the IDT gives task switching power to interrupts. This reduces operating-system involvement ininterrupt handling, and thereby reduces the time needed to respond to interrupts.The operating system normally uses a JMP instruction to a TSS descriptor to cause a task switch. ACALL instruction to a task gate in an LDT is useful for implementing coroutines.The IRET instruction exits from a nested task that is invoked by a CALL as well as from one invokedby an interrupt. (You cannot use the RET instruction to exit from a CALLed task; RET does notperform a task switch.) The NT (nested task) flag controls the function of the IRET instruction. Whena CALL (or interrupt) causes a task switch, the processor sets the NT flag as the new task begins andfills the back-link of the new TSS with the selector of the calling task's TSS. When the NT flag is set,the IRET instruction causes a task switch to the task whose TSS selector is stored in the back-link.The new task must be marked as busy (type code = 3); otherwise an exception occurs.Table 4-1. Task Switching OperationsOperationDescriptorReferencedDescriptorTableCALL, JMP, IRET TSS GOTCALL, JMP task gate GOT, LOTINT instruction,external interrupt, task gate lOTexception4-3 121960·001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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Page 36 and 37: USING HARDWARE PROTECTION FEATURES(
Page 38 and 39: USING HARDWARE PROTECTION FEATURES
Page 40 and 41: USING HARDWARE PROTECTION FEATUREST
Page 42 and 43: USING HARDWARE PROTECTION FEATURESo
Page 44 and 45: USING HARDWARE PROTECTION FEATURESL
Page 46 and 47: USING HARDWARE PROTECTION FEATUREST
Page 48 and 49: USING HARDWARE PROTECTION FEATURESE
Page 50 and 51: inl:el~USING HARDWARE PROTECTION FE
Page 52 and 53: IntelUSING HARDWARE PROTECTION FEAT
Page 54 and 55: IntelU~ING HARDWARE PROTECTION FEAT
Page 56 and 57: lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
Page 59 and 60: CHAPTER 3REAL MEMORY MANAGEMENTIn d
Page 61 and 62: REAL MEMORY MANAGEMENTIALLOCATEGATE
Page 63 and 64: interREAL MEMORY MANAGEMENTBEFOREAF
Page 65 and 66: REAL MEMORY MANAGEMENTGLOBAL DESCRI
Page 67 and 68: REAL MEMORY MANAGEMENTTable 3-1. Ac
Page 69 and 70: REAL MEMORY MANAGEMENTBEFOREI "FREE
Page 71 and 72: REAL MEMORY MANAGEMENTBEFOREI "FREE
Page 73 and 74: REAL MEMORY MANAGEMENTPL/M-286 COMP
Page 79: REAL MEMORY MANAGEMENTPL/M-286 COMP
Page 82 and 83: IIIIIIIIIIIIIIIIIIIIII
Page 86 and 87: TASK MANAGEMENTIf the proc~sser, wh
Page 88 and 89: TASK MANAGEMENTUsually, termination
Page 90 and 91: TASK MANAGEMENTTASK XTSS TSS TSS TS
Page 92 and 93: TASK MANAGEMENTSCHEDULING POLICIEST
Page 94 and 95: TASK MANAGEMENTThe example in figur
Page 96 and 97: TASK MANAGEMENTREADY QUEUESBY PRIOR
Page 98 and 99: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
Page 101 and 102: CHAPTER 5DATA SHARING, ALIASING, AN
Page 103 and 104: DATA SHARING, ALIASING, AND SYNCHRO
Page 105 and 106: interDATA SHARING, ALIASING, AND SV
Page 117: DATA SHARING, ALIASING, AND SYNCHRO
Page 121 and 122: CHAPTER 6SIGNALS AND INTERRUPTSInte
Page 123 and 124: interSIGNALS AND INTERRUPTSlOTGOTTS
Page 125 and 126: SIGNALS AND INTERRUPTSTable 6-1. In
Page 127 and 128: SIGNALS AND INTERRUPTSSend interrup
Page 129 and 130: SIGNALS AND INTERRUPTSprocedure suc
Page 131: Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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interBINDING AND LOADINGsystem-IDiA
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BIND.ING AND LOADINGConverting a Pr
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BINDING AND LOADINGThe OMF of each
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interBINDING AND LOADINGsystem-IDiA
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOADI.NGPL/M-286 COMPIL
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BINDING AND LOADINGPL/M-286 COMPILE
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BINDING AND LOADINGPL/M-2B6 COMPILE
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BINDING AND LOAD.INGPL/M-286 COMPIL
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interBINDING AND LOADINGPL/M-286 CO
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BINDING AND LOADINGPL/M-286 COMPILE
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Numerics Processor Extension 12
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NUMERICS PROCESSOR EXTENSIONMath Pr
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interNUMERICS PROCESSOR EXTENSION
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Extended Protection13
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EXTENDED PROTECTIONIndirect NamingT
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EXTENDED PROTECTIONanother procedur
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Glossary
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GLOSSARYbootloadable module: a modu
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GLOSSARYexception: a processor-dete
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GLOSSARYintersegment reference: a r
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GLOSSARYoutward call: the attempt t
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GLOSSARYscheduling state: one of se
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GLOSSARYvirtual address: an address
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INDEXES register, 2-17, 2-18, 2-21,
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INDEXpresent bit, 2-2, 2-3, 2-9, 5-
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interu.s. SALES OFFICESALAIWIA IlEQ
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interu.s. DISTRIBUTORSNEW YORK (C"n
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intJINTEL INTERNATIONAL SALES OFFIC
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iAPX 286 Operating System Writers Guide 1983

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