iAPX 286 Operating System Writers Guide 1983

TASK MANAGEMENTUsually, termination of a task is possible regardless of its scheduling state; therefore, this diagram doesnot illustrate the transition to "terminated" state.Interfacing with the Hardware SchedulerMany applications of the iAPX 286 need both software scheduling (by the operating system) andhardware scheduling (by the interrupt mechanism), but when two schedulers work with the same setof tasks, you must ensure that they work together harmoniously. Figure 4-3 illustrates the additionalcomplexity of dual schedulers.Note that scheduling state under hardware scheduling is nearly analogous to scheduling state undersoftware scheduling. The priority concept, often used in software scheduling, has its analog in thepriority mechanism implemented by the interrupt controller. The priority of hardware-scheduled tasksrelative to software-scheduled tasks is controlled by two factors:• The CPU's interrupt-enable flag (IF), and the instruction's CLI (which clears IF) and STI (whichsets IF)• The 8259A Programmable Interrupt Controller, an LSI component that allows selective maskingof interrupts so that software can prevent some external interrupts.When IF is set, all hardware-scheduled tasks whose interrupts are not masked out have higher prioritythan all software-scheduled tasks. When IF is reset, all hardware-scheduled tasks have lower prioritythan the currently executing task. Only the operating system (CPL < = IOPL) has the right to executeHARDWARE SCHEDULEDPREEMPTIVE INTERRUPTINITIATEIRETDISPATCHSOFTWARE SCHEDULED121960-27Figure 4-3. Expanded Scheduling State Transition Diagram4-6 121960-001