INDEXpresent bit, 2-2, 2-3, 2-9, 5-3, 7-5, 7-6, 9-1 thru9-5, 11-12primitives, 11-3,11 ~4, 11-6, 11-12, 11-14,13-4priority, 2-19, 4-6, 4-7, 4-9, 4-10, 6-6, 6-7privilege level, 1-3, 1-4, 1-8, 2-6, 2-7 thru 2-11,2-15,2-18,2-20,2-21,3-8,3-9,4-1,4-2,4-9,4-12,4-13,5-2,5-7,5-10,5-12,6-2,6-3,6-5,6-8,8-2,8-3,8-7,9-3,9-7, 11-2, 11-6, 11-9,11-10, 12-2, 12-4, 13-1, 13-2, 13-4, 13-5PROC, 11-4"processor extension error" exception, 7-8, 12-5"processor extension not available"exception,7-4, 12-3, 12-4"processor extension segment overrun"exception, 7-5, 12-4, 12-5profiling, 9-7, 9-8program loading, 1-8, 1-10, 2-3, 2-4, 3-1, 6-5,Chapter 11bootstrap, 1-9, 11-10protected, virtual-address mode, 10-1, 10-2, 12-2protection, 1-3 thru 1-5, 1-9, Chapter 2,3-1,3-7,4-3,4-4,4-6,5-1,5-4,5-7,5-10,6-2,6-3,6-5,6-6,7-3,8-1 thru 8-4, 8-7, Chapter 13violation, 6-4, 6-9, 7-7PUBLIC, 3-2, 3-6, 3-8, 3-9, 10-3, 11-3, 11-6PUSH,7-6PUSHA,7-7RCL, RCR, 7-8readable segment, 2-7read-only segment, 7-7real address mode, 10-1, 10-2real memory management, see memorymanagement,realrecovery, see exceptionsregion, 5-10, 9-4, 9-5REP, REPE, REPNE, 7-7requested privilege level (RPL), 2-11,2-16,7-2,13-2 thru 13-4RESERVE, 3"6, 11"6reserved word (of descriptor), 2-3, 2-22RESET, 10-1, 10-3RESTORE$GLOBAL$TABLE,2-15RESTORE$INTERRUPT$T ABLE, 2-15RESTORE$REAL$STATUS, 12-4return pointer, 6-2, Chapter 7, 12-4, 13-3return link, see return pointerreturn address, see return pointerrelocation (of segment), 2-4, 2-20, 5-2, 5-3, 5-12,8-3RET, 2-7, 2-9, 2-10, 4-3, 11-5RETURN, 11-5ROM, 10-1RPL, see requested privilege levelSAVE$GLOBAL$TABLE,2-15SA VE$INTERRUPT$TABLE, 2"15·SA VE$REAL$ST A TUS, 12-4SBB,7-8SCAS, 7-7scheduling, 2-19, 4-11, 5-12, 9-5hardware, see scheduling, interruptinterrupt, 4-6, 4-7,4-9,6-1,6-5,6-6,8-7queues, 4-12, 4-13, 9-4, 11-10, 11-14software, 4-7, 4-9, 6-1, 6-5, 6-6, 7-6state, 4-5 thru 4-7, 4-10SEGMENT, 11-4, 11-6segment, see logical segment, physical segmentsegment limit, see limit fieldsegmented architecture, 9-6SEGMENT$REAOABLE,SEGMENT$WRITABLE,13-2selector, 2-1, 2-2, 2-8, 2-9, 2-15, 2-16, 3-6,4-1,4-3,5-7,7-6,7-7,11-12,13-1parameters, 2-16, 13-1 thru 13-4null, 2-15, 2-17, 7-7SELECTOR$OF, 3-6semaphore, 5-6, 5-7, 5-10, 5-16, 9-4, 9-5, 11-2,12-4, 13-1, 13-4, 13-5send privilege level (SPL), 13-5SGOT,2-15shadow task, 6-8, 6-9sharing (of segments), 2-14,2-15,2-19,2-20,2-22,4-4, Chapter 5, 8"7, 9-5, 11-2, 1l~4,13-1,13-4,13-5shutdown, 7-5, 10-2SI register, 7-7SlOT, 2-15, 6-2signal, 4-5,5-7, 5-10, Chapter 6single-step flag (TF), 6-2, 7-3SLOT, 2-14, 9-7slot, 2-20, 2-22, 2-26, 5-10, 11-6, 11-14, 13-5SMALL,II-4SMSW, 12-1SP register, 4-2, 4-12, 7-6SPL, see send privilege levelSS register; 4-2, 4-12, 7-5 thru 7-7, 9-2, 9-6,10-1stack, 2-5, 2-8, 3-1, 4-12, 6-2, 6-4, 7-1, 7"2,7-6,7-7, 9-3, 9-4, 9-7, 10-2, 11-6, 11"9 thru11-11,13-4initial, 4-2, 4-3, 11-6overflow, 7-5, 7-7exception, 7-5 thru 7-7,9.2static system, 1-7, 1-9, 1-10,2-3,2-19,3"1,4-4,6-4, 11-9STI, 4-6, 4-7, 5-6, 6-2, 8-2STOS,7-7STR, 4-1, 4-7, 4-11Index-4 121960-001
INDEXsubsystem, 11-4swapping, 5-12, 8-3, 9-2 thru 9-4, 9-8synchronization, 2-22, 3-8, 3-9, Chapter 5, 8-4,8-6, 12-2, 13-4, 13-5system initialization, 6-5,6-6, Chapter 10TABLE,II-6table indicator (TI), 2-16, 2-17, 7-2task, 1-1creation, 2-2, 2-18, 3-1, 5-12, 6-9,11-9database (TDB), 4-11, 5-12,9-4, 11-9, 11-10,12-3, 12-4management, Chapter 4state, 4-1, 10-2, 12-3switching, 2-14, 4-1, 4-3, 4-4, 4-9, 5-6, 6-2, 7-5thru 7-7, 8-2, 9-4, 9-5, 10-2, 11-9, 12-2 thru12-4TASK, 11-6task register (TR), 4-1, 4-2, 4-4, 9-1, 10-2task state segment (TSS), 2-5, 2-14, 2-18,3-1,4-1 thru 4-4, 4-10 thru 4-13, 5-1, 6-2, 6-4,6-9,7-1,7-5,7-7,8-2,9-1,9-4 thru 9-7,10-2, 10-3, 10-5, 11-6, 11-8 thru 11-12,11-14TASK$REGISTER,4-1TDB, see task databasetermination (of task), 6-9, 7-1, 7-5, 12-5TF, see single-step flagthrashing, 9-8TI, see table indicatortime slice, 4-5, 4-9 thru 4-11timer, see 8254 Programmable Interval TimerTS (task switched) flag, 7-4, 12-1 thru 12-4TSS, see task state segmenttypefield of descriptor, 2-5,2-17,2-18,2-20,2-21,4-3,4-4,6-2,9-3, 11-10, 11-14, 13-1extended, 13-1, 13-2, 13-5UDI (Universal Development Interface), 8-1"undefined opcode" exception, 7-4 .UNIX, 11-9usage privilege level (UPL), 8-7, 13-4, 13-5vectoring, 6-1, 6-3, 7-1VERR, VERW, 13-2, 13-4virtual memory, see memory management,virtualWAIT, 7-4, 7-8,12-1 thru 12-5WAIT$FOR$INTERRUPT,4-3word count, 2-8writable data segment, 2-6, 9-5, 11-10, 11-14,13-1,13-4XOS, II-I, 11-2, 11-4, 11-6Index-5121960-001
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LITERATUREIn addition to the produc
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Intel Corporation makes no warranty
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PREFACEExternal LiteratureMany aspe
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Table of ContentsCHAPTER 1PageINTRO
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TABLE OF CONTENTSCHAPTER 9PageVIRTU
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TABLE OF CONTENTSLIST OF FIGURESFig
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Introduction to Protected 1Multitas
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INTRODUCTION TO PROTECTED MULTITASK
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inter INTRODUCTION TO PROTECTED MUL
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111'eI INTRODUCTION TO PROTECTED MU
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INTRODUCTION TO PROTECTED MULTITASK
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INTRODUCTION TO PROTECTED MULTITASK
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Using Hardware2Protection Features
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USING HARDWARE PROTECTION,FEATURESs
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interUSING HARDWARE PROTECTION FEAT
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USING HARDWARE PROTECTION FEATURES(
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USING HARDWARE PROTECTION FEATURES
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESo
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USING HARDWARE PROTECTION FEATURESL
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USING HARDWARE PROTECTION FEATUREST
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USING HARDWARE PROTECTION FEATURESE
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inl:el~USING HARDWARE PROTECTION FE
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IntelUSING HARDWARE PROTECTION FEAT
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IntelU~ING HARDWARE PROTECTION FEAT
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lSLDTFORMATRt;;SERV~~"O~iA~~.~ijij
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CHAPTER 3REAL MEMORY MANAGEMENTIn d
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REAL MEMORY MANAGEMENTIALLOCATEGATE
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interREAL MEMORY MANAGEMENTBEFOREAF
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REAL MEMORY MANAGEMENTGLOBAL DESCRI
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REAL MEMORY MANAGEMENTTable 3-1. Ac
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTBEFOREI "FREE
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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REAL MEMORY MANAGEMENTPL/M-286 COMP
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IIIIIIIIIIIIIIIIIIIIII
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II I telTASK MANAGEMENTCPUTASK REGI
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TASK MANAGEMENTIf the proc~sser, wh
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TASK MANAGEMENTUsually, termination
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TASK MANAGEMENTTASK XTSS TSS TSS TS
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TASK MANAGEMENTSCHEDULING POLICIEST
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TASK MANAGEMENTThe example in figur
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TASK MANAGEMENTREADY QUEUESBY PRIOR
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IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII
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CHAPTER 5DATA SHARING, ALIASING, AN
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DATA SHARING, ALIASING, AND SYNCHRO
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interDATA SHARING, ALIASING, AND SV
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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DATA SHARING, ALIASING, AND SYNCHRO
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CHAPTER 6SIGNALS AND INTERRUPTSInte
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interSIGNALS AND INTERRUPTSlOTGOTTS
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SIGNALS AND INTERRUPTSTable 6-1. In
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SIGNALS AND INTERRUPTSSend interrup
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SIGNALS AND INTERRUPTSprocedure suc
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Handling Exception Conditions 7
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HANDLING EXCEPTION CONDITIONSError
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HANDLING EXCEPTION CONDITIONSAn exc
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HANDLING EXCEPTION CONDITIONSA few
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HANDLING EXCEPTION CONDITIONSAn ins
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CHAPTER 8INPUT /OUTPUTMany of the c
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INPUT /OUTPUTYou can still take adv
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INPUT /OUTPUT• Only the operating
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INPUT /OUTPUTtask the I/0 procedure
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CHAPTER 9VIRTUAL MEMORYThe memory l
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VIRTUAL MEMORYthose segments that a
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VIRTUAL MEMORY• Return the RAM sp
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VIRTUAL MEMORYReplacementThe operat
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System Initialization10
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CHAPTER 10SYSTEM INITIALIZATIONThe
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SYSTEM INITIALIZATIONStarting the f
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iAPX286 "ACRO ASSEMBLERLOCOBJEnter
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iAPX286 MACRO ASSEMBLEtEnter Protec
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iAPX286 MACRO ASSEMBLER·· Enter ~
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iAPX286 'UCRO USE148LER Ente,. P,.o
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iAPX286 MACRO ASSEMBLEREnt9~ P~otec
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iAPX286 MACRO ASSEMBLE~ INITIAL TAS
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CHAPTER 11BINDING AND LOADINGBindin
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BINDING AND LOADINGNamingThe names
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BINDING AND LOADING$ COMPACT (NUCLE
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interBINDING AND LOADINGsystem-IDiA
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BIND.ING AND LOADINGConverting a Pr
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