Xilinx 4000-series FPGAs

More documents

Recommendations

Info

XC4000E and XC4000X Series Field Programmable Gate ArraysCARRYLOGICC OUTC IN DOWNDINGGCARRYHYG4G3G2G1GDINHGFS/RD QYQECC OUT0H1HFCARRYDINHGFS/RD QXQF4ECF3F2FF1HFXC UP CK S/R ECINOUTFigure 14: Fast Carry Logic in XC4000E CLB (shaded area not present in XC4000X)X66994-20 November 10, 1997 (Version 1.4)
C OUTG1M1MI00 1G2G4G3F21MC OUT0MTOFUNCTIONGENERATORSF1M00 1F4M0 1F3M31M 0MMM1 0C IN UPC IN DOWNX2000Figure 15: Detail of XC4000E Dedicated Carry LogicInput/Output Blocks (IOBs)User-configurable input/output blocks (IOBs) provide theinterface between external package pins and the internallogic. Each IOB controls one package pin and can be configuredfor input, output, or bidirectional signals.Figure 16 shows a simplified block diagram of theXC4000E IOB. A more complete diagram which includesthe boundary scan logic of the XC4000E IOB can be foundin Figure 41 on page 4-44, in the “Boundary Scan” section.The XC4000X IOB contains some special features notincluded in the XC4000E IOB. These features are highlightedin a simplified block diagram found in Figure 17, anddiscussed throughout this section. When XC4000X specialfeatures are discussed, they are clearly identified in thetext. Any feature not so identified is present in bothXC4000E and XC4000X devices.IOB Input SignalsTwo paths, labeled I1 and I2 in Figure 16 and Figure 17,bring input signals into the array. Inputs also connect to aninput register that can be programmed as either an edgetriggeredflip-flop or a level-sensitive latch.The choice is made by placing the appropriate library symbol.For example, IFD is the basic input flip-flop (rising edgetriggered), and ILD is the basic input latch (transparent-High). Variations with inverted clocks are available, andsome combinations of latches and flip-flops can be implementedin a single IOB, as described in the XACT LibrariesGuide.The XC4000E inputs can be globally configured for eitherTTL (1.2V) or 5.0 volt CMOS thresholds, using an option inthe bitstream generation software. There is a slight inputhysteresis of about 300mV. The XC4000E output levels arealso configurable; the two global adjustments of inputthreshold and output level are independent.Inputs on the XC4000XL are TTL compatible and 3.3VCMOS compatible. Outputs on the XC4000XL are pulled tothe 3.3V positive supply.The inputs of XC4000 Series 5-Volt devices can be drivenby the outputs of any 3.3-Volt device, if the 5-Volt inputs arein TTL mode.Supported sources for XC4000 Series device inputs areshown in Table 9.November 10, 1997 (Version 1.4) 4-21
Page 1 and 2: ook1®XC4000E and XC4000X SeriesFie
Page 3 and 4: XC4000E and XC4000X SeriesCompared
Page 5 and 6: Detailed Functional DescriptionXC40
Page 8 and 9: XC4000E and XC4000X Series Field Pr

Xilinx 4000-series FPGAs

Create successful ePaper yourself

Delete template?

Save as template?