Xilinx 4000-series FPGAs

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XC4000E and XC4000X Series Field Programmable Gate ArraysQuadSingleDoubleLongCLBDirectConnectLongQuadLongGlobalClockLong Double Single GlobalClockCarryChainDirectConnectx5994Figure 26: High-Level Routing Diagram of XC4000 Series CLB (shaded arrows indicate XC4000X only)Table 15: Routing per CLB in XC4000 Series DevicesXC4000EXC4000XVertical Horizontal Vertical HorizontalSingles 8 8 8 8Doubles 4 4 4 4Quads 0 0 12 12Longlines 6 6 10 6Direct 0 0 2 2ConnectsGlobals 4 0 8 0Carry Logic 2 0 1 0Total 24 18 45 32DoubleSinglesDoubleDoubleSinglesDoubleSix Pass TransistorsPer Switch MatrixInterconnect PointX6600Figure 27: Programmable Switch Matrix (PSM)Programmable Switch MatricesThe horizontal and vertical single- and double-length linesintersect at a box called a programmable switch matrix(PSM). Each switch matrix consists of programmable passtransistors used to establish connections between the lines(see Figure 27).For example, a single-length signal entering on the rightside of the switch matrix can be routed to a single-lengthline on the top, left, or bottom sides, or any combinationthereof, if multiple branches are required. Similarly, a double-lengthsignal can be routed to a double-length line onany or all of the other three edges of the programmableswitch matrix.Single-Length LinesSingle-length lines provide the greatest interconnect flexibilityand offer fast routing between adjacent blocks. Thereare eight vertical and eight horizontal single-length linesassociated with each CLB. These lines connect the switchingmatrices that are located in every row and a column ofCLBs.Single-length lines are connected by way of the programmableswitch matrices, as shown in Figure 29. Routingconnectivity is shown in Figure 28.Single-length lines incur a delay whenever they go througha switching matrix. Therefore, they are not suitable for routingsignals for long distances. They are normally used toconduct signals within a localized area and to provide thebranching for nets with fanout greater than one.4-30 November 10, 1997 (Version 1.4)
QUADDOUBLESINGLEDOUBLELONGF4 C4 G4G1C1F1KXXQCLBYQYG3C3F3F2 C2 G2DIRECTFEEDBACKLONGLONGGLOBALDOUBLELONGLONGDOUBLEGLOBALDIRECTQUADSINGLEFEEDBACKCommon to XC4000E and XC4000XXC4000X onlyProgrammable Switch MatrixFigure 28: Detail of Programmable Interconnect Associated with XC4000 Series CLBNovember 10, 1997 (Version 1.4) 4-31
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Page 3 and 4: XC4000E and XC4000X SeriesCompared
Page 5 and 6: Detailed Functional DescriptionXC40
Page 8 and 9: XC4000E and XC4000X Series Field Pr

Xilinx 4000-series FPGAs

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