Xilinx 4000-series FPGAs

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XC4000E and XC4000X Series Field Programmable Gate ArraysCLBCLBCLBDoublesCLBCLBCLBPSMPSMSinglesDoublesCLB CLB CLBCLBCLBCLBPSMPSMCLB CLB CLBCLBCLBCLBFigure 29: Single- and Double-Length Lines, withProgrammable Switch Matrices (PSMs)Double-Length LinesThe double-length lines consist of a grid of metal segments,each twice as long as the single-length lines: they run pasttwo CLBs before entering a switch matrix. Double-lengthlines are grouped in pairs with the switch matrices staggered,so that each line goes through a switch matrix atevery other row or column of CLBs (see Figure 29).There are four vertical and four horizontal double-lengthlines associated with each CLB. These lines provide fastersignal routing over intermediate distances, while retainingrouting flexibility. Double-length lines are connected by wayof the programmable switch matrices. Routing connectivityis shown in Figure 28.Quad Lines (XC4000X only)XC4000X devices also include twelve vertical and twelvehorizontal quad lines per CLB row and column. Quad linesare four times as long as the single-length lines. They areinterconnected via buffered switch matrices (shown as diamondsin Figure 28 on page 4-31). Quad lines run past fourCLBs before entering a buffered switch matrix. They aregrouped in fours, with the buffered switch matrices staggered,so that each line goes through a buffered switchmatrix at every fourth CLB location in that row or column.(See Figure 30.)The buffered switch matrixes have four pins, one on eachedge. All of the pins are bidirectional. Any pin can drive anyor all of the other pins.Each buffered switch matrix contains one buffer and sixpass transistors. It resembles the programmable switchmatrix shown in Figure 27, with the addition of a programmablebuffer. There can be up to two independent inputsX6601Figure 30: Quad Lines (XC4000X only)and up to two independent outputs. Only one of the independentinputs can be buffered.The place and route software automatically uses the timingrequirements of the design to determine whether or not aquad line signal should be buffered. A heavily loaded signalis typically buffered, while a lightly loaded one is not. Onescenario is to alternate buffers and pass transistors. Thisallows both vertical and horizontal quad lines to be bufferedat alternating buffered switch matrices.Due to the buffered switch matrices, quad lines are veryfast. They provide the fastest available method of routingheavily loaded signals for long distances across the device.LonglinesX9014Longlines form a grid of metal interconnect segments thatrun the entire length or width of the array. Longlines areintended for high fan-out, time-critical signal nets, or netsthat are distributed over long distances. In XC4000Xdevices, quad lines are preferred for critical nets, becausethe buffered switch matrices make them faster for high fanoutnets.Two horizontal longlines per CLB can be driven by 3-stateor open-drain drivers (TBUFs). They can therefore implementunidirectional or bidirectional buses, wide multiplexers,or wired-AND functions. (See “Three-State Buffers” onpage 4-27 for more details.)Each horizontal longline driven by TBUFs has either two(XC4000E) or eight (XC4000X) pull-up resistors. To activatethese resistors, attach a PULLUP symbol to the longlinenet. The software automatically activates the appropriatenumber of pull-ups. There is also a weak keeper ateach end of these two horizontal longlines. This circuit pre-4-32 November 10, 1997 (Version 1.4)
vents undefined floating levels. However, it is overridden byany driver, even a pull-up resistor.Each XC4000E longline has a programmable splitter switchat its center, as does each XC4000X longline driven byTBUFs. This switch can separate the line into two independentrouting channels, each running half the width or heightof the array.Each XC4000X longline not driven by TBUFs has a bufferedprogrammable splitter switch at the 1/4, 1/2, and 3/4points of the array. Due to the buffering, XC4000X longlineperformance does not deteriorate with the larger arraysizes. If the longline is split, the resulting partial longlinesare independent.Routing connectivity of the longlines is shown in Figure 28on page 4-31.Direct Interconnect (XC4000X only)The XC4000X offers two direct, efficient and fast connectionsbetween adjacent CLBs. These nets facilitate a dataflow from the left to the right side of the device, or from thetop to the bottom, as shown in Figure 31. Signals routed onthe direct interconnect exhibit minimum interconnect propagationdelay and use no general routing resources.The direct interconnect is also present between CLBs andadjacent IOBs. Each IOB on the left and top device edgeshas a direct path to the nearest CLB. Each CLB on the rightand bottom edges of the array has a direct path to the nearesttwo IOBs, since there are two IOBs for each row or columnof CLBs.The place and route software uses direct interconnectwhenever possible, to maximize routing resources and minimizeinterconnect delays.I/O RoutingXC4000 Series devices have additional routing around theIOB ring. This routing is called a VersaRing. The VersaRingfacilitates pin-swapping and redesign without affectingboard layout. Included are eight double-length lines spanningtwo CLBs (four IOBs), and four longlines. Global linesand Wide Edge Decoder lines are provided. XC4000Xdevices also include eight octal lines.A high-level diagram of the VersaRing is shown inFigure 32. The shaded arrows represent routing presentonly in XC4000X devices.Figure 34 on page 4-35 is a detailed diagram of theXC4000E and XC4000X VersaRing. The area shownincludes two IOBs. There are two IOBs per CLB row or column,therefore this diagram corresponds to the CLB routingdiagram shown in Figure 28 on page 4-31. The shadedareas represent routing and routing connections presentonly in XC4000X devices.Octal I/O Routing (XC4000X only)Between the XC4000X CLB array and the pad ring, eightinterconnect tracks provide for versatility in pin assignmentand fixed pinout flexibility. (See Figure 33 on page 4-34.)These routing tracks are called octals, because they can bebroken every eight CLBs (sixteen IOBs) by a programmablebuffer that also functions as a splitter switch. The buffersare staggered, so each line goes through a buffer at everyeighth CLB location around the device edge.The octal lines bend around the corners of the device. Thelines cross at the corners in such a way that the segmentmost recently buffered before the turn has the farthest distanceto travel before the next buffer, as shown inFigure 33.IOBIOBIOBIOBIOBIOBIOBIOBIOBIOBCLB~ ~CLB~ ~ ~ ~CLB~ ~CLBCLB~ ~CLBIOBIOBIOBIOBIOBIOBIOBIOBIOBIOBX6603Figure 31: XC4000X Direct InterconnectNovember 10, 1997 (Version 1.4) 4-33
Page 1 and 2: ook1®XC4000E and XC4000X SeriesFie
Page 3 and 4: XC4000E and XC4000X SeriesCompared
Page 5 and 6: Detailed Functional DescriptionXC40
Page 8 and 9: XC4000E and XC4000X Series Field Pr

Xilinx 4000-series FPGAs

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