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Xilinx 4000-series FPGAs

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XC<strong>4000</strong>E and XC<strong>4000</strong>X Series Field Programmable Gate ArraysIOBWEDWEDQuadSingleINTERCONNECTDoubleLongIOBWEDDirectConnectLongDirectConnectEdge Double LongDecodeGlobalClockOctalFigure 32: High-Level Routing Diagram of XC<strong>4000</strong> Series VersaRing (Left Edge)WED = Wide Edge Decoder, IOB = I/O Block (shaded arrows indicate XC<strong>4000</strong>X only)X5995IOBIOBIOBIOBSegment with nearest bufferconnects to segment with furthest bufferFigure 33: XC<strong>4000</strong>X Octal I/O RoutingX90154-34 November 10, 1997 (Version 1.4)

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