PHYSIOLOGICAL-READOUT

SESSION 1
Monday February 6 th , 8:30 AM
Plenary Session — Invited Papers
Chair: Anantha Chandrakasan, Massachusetts Institute of Technology, Cambridge, MA
ISSCC Conference Chair
Associate Chair: Boris Murmann, Stanford University, Stanford, CA
ISSCC International Technical-Program Chair
FORMAL OPENING OF THE CONFERENCE
8:30 AM
1.1 A Smart Design Paradigm for Smart Chips 8:45 AM
Cliff Hou,Vice President, Research & Development, TSMC, Hsinchu, Taiwan
The world requires more specialized smart chips for connecting people intelligently at all
times. Requirements for such chips in computing capability, power consumption, and form
factor are becoming ever more demanding, while the market window is significantly shrinking.
This talk explores the trends in chip innovation from costly multi-chip and SoC solutions to
separated chips combined with wafer-stacking or 3-D packaging. These trends are further
driving system-level integration for improved chip and systems performance, cycle time, and
costs.
To capitalize on such mega-trends, innovations extending Moore’s Law and efforts on specialty
technologies for advancing connectivity are discussed. The ultimate goal is to optimize
system performance through system-level integration of functionalities in advanced 3-D
packaging. These will introduce new design challenges, where possible solutions are further
gated by learning curves and cycle times.
Smart-chip designers are increasingly looking for opportunities where others can supply
expertise and assets, whether as single-chip designs or system-level integrations. We
highlight the emergence of a new collaborative paradigm, which is moving from technologycentric
options to total platform-centric solutions sufficiently broad to address the unique
challenges of the next big things, particularly in mobile, IoT, automotive, high-performance
computing.
1.2 Dynamics of Exponentials in Circuits and Systems 9:20 AM
Ahmad Bahai, Chief Technology Officer, Texas Instruments, Santa Clara, CA
Astonishing progress in semiconductor devices, circuits, and manufacturing has prompted
an unprecedented revolution in electronics. “Things” are getting smarter and more connected,
with higher semiconductor content. Smart personal electronics, autonomous systems, and
smart factories are prime examples.
These impressive developments are fueled by the power of exponentials: CMOS scaling,
efficiency of semiconductor manufacturing, the bandwidth efficiency of communication
systems, and total network capacity have all been doubling almost every two years! The sheer
scaling of CMOS has dominated the challenges and promises of advanced IC design.
Advanced digital-intensive designs count on denser, faster, and cheaper switches. Along the
way, analog and RF designs have creatively embraced the challenge of implementing analog
topologies on digitally-optimized processes.
The present slowdown of the CMOS scaling trend brings exciting opportunities for “multidimensional
innovations” in circuits and systems: The continuing demand for higher
performance, in many applications, will further tilt solutions toward creative system and circuit
topologies. Many emerging complementary technologies such as MEMS-based sensors and
timing references, III-V devices, high-performance SiGe devices, and silicon photonics, will
not necessarily integrate with CMOS monolithically. However, they enable opportunities for
system repartitioning and new circuit topologies in applications such as sensing, power, high
voltage, high-performance RF, and precision timing.
CMOS is here to stay for the foreseeable future! It will simply coexist synergistically with
emerging technologies. This talk will discuss opportunities in “multi-dimensional innovation”
that will make the future of the field less predictable.....but even more interesting and exciting!
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