PHYSIOLOGICAL-READOUT

SESSION 29
Wednesday February 8 th , 1:30 PM
Optical- and Electrical-Link Innovations
Session Chair: Sam Palermo, Texas A&M University, College Station, TX
Associate Chair: Hideyuki Nosaka, NTT, Atsugi, Japan
1:30 PM
29.1 A 64Gb/s 1.4pJ/b NRZ Optical-Receiver Data-Path in 14nm CMOS FinFET
A. Cevrero 1 , I. Ozkaya 1,3 , P. A. Francese 1 , C. Menolfi 1 , T. Morf 1 , M. Brandli 1 , D. Kuchta 2 ,
L. Kull 1 , J. Proesel 2 , M. Kossel 1 , D. Luu 1 , B. Lee 2 , F. Doany 2 , M. Meghelli 2 , Y. Leblebici 3 ,
T. Toifl 1
1
IBM Research, Rueschlikon, Switzerland; 2 IBM Research, Yorktown Heights, NY
3
EPFL, Lausanne, Switzerland
2:00 PM
29.2 A Transmitter and Receiver for 100Gb/s Coherent Networks with
Integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOS
J. Cao, D. Cui, A. Nazemi, T. He, G. Li, B. Catli, M. Khanpour, K. Hu, T. Ali, H. Zhang,
H. Yu, B. Rhew, S. Sheng, Y. Shim, B. Zhang, A. Momtaz
Broadcom, Irvine, CA
2:30 PM
29.3 A 40Gb/s PAM-4 Transmitter Based on a Ring-Resonator Optical DAC in
45nm SOI CMOS
S. Moazeni 1 , S. Lin 1 , M. T. Wade 2 , L. Alloatti 3 , R. J. Ram 4 , M. A. Popovic 5 , V. Stojanovic 1
1
University of California, Berkeley, CA; 2 Ayar Labs, San Francisco, CA
3
ETH Zurich, Zurich, Switzerland
4
Massachusetts Institute of Technology, Cambridge, MA
5
Boston University, Boston, MA
Break 3:00 PM
3:15 PM
29.4 A 16Gb/s 3.6pJ/b Wireline Transceiver with Phase Domain Equalization
Scheme: Integrated Pulse Width Modulation (iPWM) in 65nm CMOS
A. Ramachandran, A. Natarajan, T. Anand, Oregon State University, Corvallis, OR
3:45 PM
29.5 12Gb/s Over Four Balanced Lines Utilizing NRZ Braid Clock Signaling
with 100% Data Payload and Spread Transition Scheme for 8K UHD
Intra-Panel Interfaces
Y. Lee, Y. Choi, S-G. Bae, J. Jun, J. Song, S. Hwang, C. Kim
Korea University, Seoul, Korea
4:15 PM
29.6 A 3-to-10Gb/s 5.75pJ/b Transceiver with Flexible Clocking in 65nm
CMOS
R. K. Nandwana 1 , S. Saxena 2 , A. Elkholy 1 , M. Talegaonkar 1 , J. Zhu 1 , W-S. Choi 1 ,
A. Elmallah 1 , P. K. Hanumolu 1
1
University of Illinois, Urbana, IL; 2 IIT Madras, Chennai, India
4:45 PM
29.7 A 2.5GHz Injection-Locked ADPLL with 197fs rms Integrated Jitter and
-65dBc Reference Spur Using Time-Division Dual Calibration
S. Kim 1 , H-G. Ko 1 , S-Y. Cho 1 , J. Lee 1 , S. Shin 1 , M-S. Choo 1 , H. Chi 2 , D-K. Jeong 1
1
Seoul National University, Seoul, Korea; 2 SK hynix, Icheon, Korea
Conclusion 5:00 PM
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