PHYSIOLOGICAL-READOUT

TUTORIALS
10:30 AM
T6 Signal Integrity Analysis for Gb/s Links
Tony Chan Carusone, University of Toronto, Toronto, Canada
Signal integrity analysis permits circuit designers to model and evaluate high-speed I/O with
fast simulations, both for quick evaluation of design alternatives and accurate high-level
verification. This tutorial covers theoretical underpinnings and practical tools for behavioral
modeling and simulation of wireline chip-to-chip links. Attendees will learn to accurately
model lossy interconnects, packaging parasitics, and transceiver front-ends. The tutorial will
also introduce nondeterministic impairments such as noise and jitter, and the modeling of
linear and decision-feedback equalization. Analysis techniques amenable to both circuit-level
(netlist) simulators and high-level modeling (e.g. Matlab) tools will be covered.
Tony Chan Carusone is a professor at the University of Toronto and occasional consultant to
industry. He co-authored the 2nd edition of the book “Analog Integrated Circuit Design” and
6 best papers at Solid-State Circuits Society conferences. He is currently a Distinguished
Lecturer for the SSCS.
T7
1:30 PM
Design Trade-Offs in Digital Intensive PLLs
Ping-Ying Wang, CMOS-Crystal, Hsinchu, Taiwan
Sunday February 5 th
The tutorial will give a comprehensive overview and provide an intuitive understanding of
digital PLLs in spatial domain. Operating principles and limitations of digital PLLs are
demonstrated by introducing an architecture-independent model with numerical calculations
in the time domain. Various digital PLL architectures, including all-digital and hybrid PLLs
are presented, followed by design strategies for building blocks, such as digital loop filters
with latency cancellation, numerically-controlled oscillators with suppression of quantization
error, digitally-controlled oscillators with all-digital supply regulation and time-to-digital
converters with time amplifiers. Finally, all-digital self-calibration techniques and digitallyassisted
PLLs are discussed.
Ping-Ying Wang received the M.S. degree in physics science from National Taiwan University,
Taipei, Taiwan, in 1994. From 1999 to 2003 he worked at Etron and Realtek, Taiwan,
developing all-digital PLLs and spread-spectrum clocking. In 2003, He joined Mediatek,
Taiwan, where he developed all-digital CDR for high-speed serial links, hybrid PLLs and alldigital
self-calibration techniques for PLL-based modulators. From 2010 to 2014, he was
technical director for the Mixed-Signal Design Division working on all-digital regulation
techniques and all-digital charge pumps for PLLs. Currently, he is co-founder of a company,
CMOS-Crystal, focused on PLLs integrated with crystal amplifiers. He holds over 36 granted
patents, and has published over 23 peer-reviewed journal and conference papers. He serves
on the IEEE International Solid-State Circuits Conference DCT subcommittee.
1:30 PM
T8 Fundamentals of Class-D Amplifier Design
Xicheng Jiang, Broadcom, Irvine, CA
Class-D amplifiers, or switching amplifiers, are popular components in mixed-signal IC design
and widely adopted for smart phones and tablets with rich multimedia thanks to their highefficiency
and high-output power capability. Their applications range from audio and video
drivers to envelope tracking for power amplifiers. In this tutorial, Class-D amplifier
fundamentals and the design of a CMOS high-performance Class-D amplifier will be covered.
Topics include 1) an overview of amplifier topologies, such as Class-A, Class-AB, Class-D,
Class-G, and Class-H; 2) architecture trade-offs; 3) comparisons of linear amplifiers and
switching amplifiers and different modulation schemes; 4) analog implementations vs. digital
implementations; and 5) detailed implementations of building blocks and the state-of-the-art
of designs. Practical design examples are used throughout the presentation. Advanced topics
include Pop-click suppression, EMI reduction, and speaker protection.
6