PHYSIOLOGICAL-READOUT

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FORUM 5 Thursday February 9 th , 8:00 AM F5: Wireline Transceivers for Mega Data Centers: 50Gb/s and Beyond Organizer: Committee: Yohan Frans, Xilinx, San Jose, CA Ichiro Fujimori, Broadcom, Irvine, CA Seung-Jun Bae, Samsung, Gyenggi, Korea Sam Palermo, Texas A&M University, College Station, TX Hideyuki Nosaka, NTT, Atsugi, Japan Simone Erba, STMicroelectronics, Pavia, Italy With the explosive data growth due to HD video content, IoT, and the rapid shift from enterprise to cloud computing, Mega Data Centers have become an essential part of the global network infrastructure. Despite their massive scale, Data Center architectures require software-defined network capability and scalability, with lower latency. Interconnects will need to support diversified media-types, higher data-rates (>50Gb/s per lane), and longer distance (up to 2km) to achieve this and still make economic sense. Once a niche for mainly VCSEL links in HPC, “Optical Ethernet” is now becoming mainstream as interconnects for both MMF and SMF in various fiber configurations are being defined within the standards. Also, copper links including backplane continue to be the interconnect with highest volume. The Forum will cover various wireline transceivers enabling Mega Data Centers such as ADC-based transceivers and Silicon Photonics, and challenges moving forward. Forum Agenda Time: Topic: 8:00 AM Breakfast 8:20 AM Introduction 8:30 AM Hyper-Scale Data Center – Pushing Bandwidth Requirements Mike Andrewartha, Microsoft, Redmond, WA 9:20 AM 256GB/s High-Bandwidth Memory Interface for Next-Generation Data Center Kyomin Sohn, Samsung Electronics, Hwaseong-si, Korea 10:10 AM Break 10:35 AM 25-to-50Gb/s Mixed-Signal Wireline Transceiver for Copper Backplane and Cable Interconnects Parag Upadhyaya, Xilinx, San Jose, CA 11:25 AM 50Gb/s+ ADC/DAC-Based Wireline Transceivers Aaron Buchwald, Inphi, Santa Clara, CA 12:15 PM Lunch 1:20 PM VCSEL-Based Transceivers for MMF Data-Center Interconnects Thé Linh Nguyen, Finisar, Sunnyvale, CA 2:10 PM Silicon Photonics Platform for 50G Optical Interconnects Michal Rakowski, imec, Leuven, Belgium 3:00 PM Break 3:20 PM For Ultra-Dense Silicon Photonic Interconnect: Hybrid Integration and Electrical-Optical Co-Design Akinori Hayakawa, Photonics Electronics Technology Research Association, Atsugi, Kanagawa, Japan 4:10 PM Large-Scale Electronic/Photonic Integration to Transform Future Data Centers Clint Schow, University of California, Santa Barbara, Santa Barbara, CA 5:00 PM Concluding Remarks 52
FORUM 6 Thursday February 9 th , 8:00 AM F6: Pushing the Performance Limit in Data Converters Organizers: Moderator: Committee: Venkatesh Srinivasan, Texas Instruments, Dallas, TX Kostas Doris, NXP Semiconductors, Eindhoven, The Netherlands David Robertson, Analog Devices, Wilmington, MA Seung-Tak Ryu, KAIST, Daejeon, Korea Seng-Pan U. (Ben), University of Macau, Macau, China Data converters continue to push the boundaries of performance by achieving higher sampling speeds and wider bandwidths. In today’s data converters, GS/s is starting to become common-place. This forum brings together experts from industry and academia to talk about recent advancements that have enabled these breakthroughs. These experts will present the state-of-the-art and address design challenges pertaining to a wide range of topics (GS/s pipes & multi-GHz sampling in DS Modulators, high-speed SAR ADCs, high-speed DACs, hybrid data converters and time-domain converters). The forum will conclude with a panel discussion with the speakers. Forum Agenda Time: Topic: 8:00 AM Breakfast + Forum Opening 8:30 AM Pushing the Boundaries of Performance – A Technology Perspective Marcel J.M. Pelgrom, Pelgrom Consult, Helmond, The Netherlands 9:20 AM Wideband GHz-Sampling ΔΣ Modulators for Wireless Communications Muhammed Bolatkale, NXP Semiconductors, Eindhoven, The Netherlands 10:10 AM Break 10:35 AM Design Techniques for Multi-GS/s and High-Performance Pipelined ADCs Manar El-Chammas, Texas Instruments, Dallas, TX 11:25 AM Advanced SAR ADCs for High-Throughput Applications Ron Kapusta, Analog Devices, Wilmington, MA 12:15 PM Lunch 1:20 PM High Speed Linear Digital-to-Analog Converters Arthur H.M. van Roermund, Eindhoven University of Technology, Eindhoven, The Netherlands 2:10 PM Best of Both Worlds – Hybrid Data Converters Michael Flynn, University of Michigan, Ann Arbor, MI 3:00 PM Break 3:20 PM Quantizing Time: Time-Domain Converters SeongHwan Cho, KAIST, Daejeon, Korea 4:10 PM Panel Discussion – Q&A, Moderator: David Robertson, Analog Devices, Wilmington, MA 5:00 PM Closing Remarks 53
Page 1 and 2: ADVANCE PROGRAM THURSDAY ALL-DAY 4
Page 3 and 4: TABLE OF CONTENTS Tutorials .......
Page 5 and 6: TUTORIALS Sunday February 5 th Long
Page 7 and 8: TUTORIALS Sunday February 5 th Xich
Page 9 and 10: FORUM 2 Sunday February 5 th , 8:00
Page 11 and 12: EVENING EVENT Sunday February 5 th
Page 13 and 14: SESSION 1 Monday February 6 th , 9:
Page 19 and 20: Demonstration Session 1, Monday Feb
Page 21 and 22: SESSION 7 Tuesday February 7 th , 8
Page 23 and 24: SESSION 9 Tuesday February 7 th , 8
Page 25 and 26: SESSION 11 Tuesday February 7 th ,
Page 29 and 30: SESSION 15 Innovations in Technolog
Page 34 and 35: Demonstration Session 2, Tuesday, F
Page 36 and 37: SESSION 18 Wednesday February 8 th
Page 48 and 49: SHORT COURSE Thursday February 9 th
Page 50 and 51: FORUM 3 Thursday February 9 th , 8:
Page 54 and 55: INTERNATIONAL TECHNICAL PROGRAM COM
Page 60 and 61: CONFERENCE INFORMATION SSCS Members
Page 62 and 63: CONFERENCE INFORMATION EVENT PHOTOG
Page 64: 445 Hoes Lane P.O. Box 1331 Piscata

PHYSIOLOGICAL-READOUT

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