PHYSIOLOGICAL-READOUT

SHORT COURSE
Thursday February 9 th , 8:00 AM
Ultra-Low-Power Analog Design
Time: Topic:
8:00 AM Breakfast
8:20 AM Introduction by Chair, Daniel Friedman
IBM Thomas J. Watson Research Center, Yorktown Heights, NY
8:30 AM MOSFET Modeling for Ultra-Low-Power Analog
Christian Enz, EPFL, Neuchatel, Switzerland
10:00 AM Break
10:30 AM Integrated DC-DC Converters for Low-Power Applications:
From Discrete Towards Fully-Integrated-CMOS Power Management
Michiel Steyaert, KU Leuven, Leuven, Belgium
12:15 PM Lunch
1:20 PM Ultra-Low-Power References and Oscillators
Dennis Sylvester, University of Michigan, Ann Arbor, MI
2:50 PM Break
3:20 PM Micropower ADCs
Kofi Makinwa, Delft University of Technology, Delft, The Netherlands
4:50 PM Conclusion
Introduction
A critical dominant trend in the evolution of the electronics industry is the incredible growth in the
sheer number of devices that are being deployed annually across a wide range of applications.
Many of these devices are being leveraged to provide interfaces between the analog world and the
digital infrastructure that supports the Internet of Everything, providing environmental sensing data
to drive more effective pollution management, component data to enhance equipment lifetime and
automate repair scheduling, process data to improve manufacturing effectiveness, and much, much
more. The proliferation of devices also extends to enabling health care applications, improved
logistics capability, and, very broadly, enabling the optimization of compute workloads across
complete application stacks. Low power analog circuits are the critical enablers for such
applications, and nano-powered analog circuits are and will be the critical enablers for a further
wide range of emerging applications.
In this short course, we explore ultra-low power analog circuits from modeling strategies to their
implementation in the context of critically significant macro-level elements. The first presentation
examines modeling approaches suited to ultra-low power analog design, describing the
methodology in the context of several deep submicron processes. Circuit design examples are
used extensively in the presentation to clarify the presented concepts. The second presentation
takes up a key block in any low power system, namely, the DC-DC converter, with primary focus on
the path from bulky to compact regulator solutions that enable the penetration of electronics into
an ever-widening set of applications. The third presentation focuses on references and oscillators,
both of which are central to almost any low-power electronic implementation. Key elements
discussed in detail include ultra-low power bandgap circuits and ultra-low power timer
implementations. Finally, the last presentation turns to the challenge of micropower data converters,
which must provide an efficient interface between the analog world and the digital back end for a
host of applications. The presentation interleaves the discussion of core ultra-low power techniques
with design examples that elucidate these techniques. Broadly, the four presentations explore ultralow
power analog design, an integral part of creating efficient, pervasive solutions for the problems
of today and tomorrow.
8:30 AM SC1: MOSFET Modeling for Ultra-Low-Power Analog
Christian Enz, EPFL, Neuchatel, Switzerland
The emergence of the IoT poses stringent requirements on the energy consumption and has
hence become the primary driver for ultra-low-power circuit design. Implementation of
complex functions under highly constrained power and area budgets makes analog and RF
circuit design ever more challenging. Some guidance would therefore be invaluable for the
designer to navigate the design space.
This short course presents simple MOSFET models that can be applied to design of ultralow-power
analog and RF. It starts with the presentation of the concept of inversion coefficient
IC as an essential design parameter that spans the entire range of operating points from weak
to strong inversion. Several figures-of-merit (FOM) capturing the various trade-offs
encountered in analog and RF circuit design are presented and compared to measurements
of 40nm and 28nm CMOS processes. Finally, a simple technique to extract the basic model
parameters is described before concluding.
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