2.2 BSP Rel. 1.0 for PPMC-275 Programmer's Guide

API Call Reference List of APIs
Table 14:MPSC Main Structure: MPSC_MAIN_STRUCT (cont.)
Bits Field Bit
Width
Description
26:25 RCDV 2 Receive Clock Divider
Defines the receive clock divider. The
receive bit rate is the rate of the clock
entering the MPSC Rx machine (from
external pin or a BRG) divided by the
RCDV field. For FM0, FM1, Manchester,
and Differential Manchester, one of the
8x, 16x, or 32x options must be set.
00 - 1x clock mode (Default. For NRZ
and NRZI only.)
01 - 8x clock mode
10 - 16x clock mode
11 - 32x clock mode
24:23 RSYL 2 Receive Sync Length (BISYNC and
Transparent Modes)
00 - External sync (CD* assertion)
01 - 4-bit sync
10 - 8-bit sync (MonoSYNC)
11 - 16-bit sync (BISYNC)
VxWorks 5.5/Tornado 2.2 BSP Rel. 1.0 for PPMC-275 5 - 77