2.2 BSP Rel. 1.0 for PPMC-275 Programmer's Guide

List of APIs API Call Reference
Execution Flow
Driver Initialization
This interrupt controller introduces full support for the CPU interrupt
lines driven by the MV-64360. It also supports the Select Register
used by the MV-64360 for minimizing the interrupt
identification process to a single read cycle. This support is provided
by an individual ISR for each MV-64360 interrupt output
pin. As the Power PC architecture is restricted to only one external
interrupt pin, this driver has the following handlers:
Table 5:Handlers
Handler Description
GtIntCpuHigh() Handles the interrupts asserted by the
CPU pin and interrupt events which are
generated by the CPU High Interrupt
Cause register.
GtIntCpuLow() Handles the interrupts asserted by the
CPU pin and interrupt events which are
generated by the CPU Low Interrupt
Cause register.
GtIntCpuSelect()
Handles the interrupts asserted by the
CPU pin and interrupt events which are
generated by the CPU High or the Low
Interrupt Cause registers (or both),
using one read cycle.
Each of these handlers has its own data structure, which holds a
list of ISRs to invoke in case of an interrupt pending on its corresponding
pin. As the Power PC architecture restrict only one external
interrupt pin, this driver uses the gtIntCpuSelect()
handler.
The driver's handlers are connected to the Power PC external
exception vector 0x500 using the VxWorks connecting routine
excIntConnect(). The user can decide which ISR to connect to
the CPU interrupt pin (gtIntCpuHigh, gtIntCpuLow or
gtIntCpuselect). As the Power PC architecture is restricted to
only one external interrupt pin, and this driver handles all MV
interrupts (High and Low), this driver makes use of the gtIntCpuSelect()
handler.
5 - 8 VxWorks 5.5/Tornado 2.2 BSP Rel. 1.0 for PPMC-275