2.2 BSP Rel. 1.0 for PPMC-275 Programmer's Guide

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List of APIs API Call Reference MV-64360 INTERRUPT CONTROLLER An interrupt controller is necessary because numerous MV-64360 interrupts share the same physical line. Hooking an Interrupt Service Routine (ISR) to this controller requires knowledge of the various GT interrupt causes. This Interrupt Controller supports a connection to the CPU interrupt line. The MV-64360 Interrupt Controller system introduces two layers of Cause registers: First Layer Second Layer FIRST LAYER This layer includes the Main High Interrupt Cause and Main Low Interrupt Cause registers. (The Select register reflects both High and Low Cause registers). This layer summarizes the interrupts generated by each MV-64360 subunit. Each bit set in these registers implies that a non-masked interrupt has occurred in a subunit. SECOND LAYER This layer includes all MV-64360 subunit's Cause registers. Each subunit has its own Cause and Mask registers. Once an interrupt event occurs, its corresponding bit in the cause register is set to "1". If the interrupt is not masked, it is also marked in the Main Interrupt Cause register (First layer). This architecture implies a unique interrupt controller for each MV-64360 subunit. INTERRUPT CONTROLLER PHASES Note: This interrupt controller introduces support only for First Layer interrupts and consists of three phases. The controller interface also provides MV64360 interrupt masking ability for the First Layer. Table 4:Interrupt Controller Phases Phase Description Driver Initialization This phase includes hooking the driver’s ISR to the CPU interrupt vector. 5 - 6 VxWorks 5.5/Tornado 2.2 BSP Rel. 1.0 for PPMC-275
API Call Reference List of APIs Software Modules Software Requirements Restrictions Table 4:Interrupt Controller Phases Phase Description ISR Connecting This phase includes the gathering of information about user/subunit ISR and interrupt priority. Interrupt handling This includes the handling of an interrupt by the Interrupt Handlers (driver's ISR). This controller prevents halt of the CPU caused by an interrupt that was enabled while no service routine was connected. In addition, there is full interrupt masking control over the MV First Layer interrupts. The software modules are: gtIntControl.c gtIntControl.h The software requirements are: WindRiver VxWorks Operating System, Version 5.3.1 or later MV General Driver This Interrupt Controller driver supports the First layer of the MV- 64360 Interrupt Controller. Thus each of the Second Layer interrupts should be handled in its own unit. Interrupt acknowledgement is NOT the responsibility of this driver. The First Layer Cause registers are Read Only. To acknowledge an interrupt, the software needs to clear (write 0) the active bit(s) in the Second Layer Cause register. VxWorks 5.5/Tornado 2.2 BSP Rel. 1.0 for PPMC-275 5 - 7
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A Appendix
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Memory Map Memory Map The following
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PCI Boot Procedure on PPMC-275 4. F
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void gtUartBaudRateChange() 5-155 v
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Product Error Report Product: Seria
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